Auto-referenced memory cell read techniques
Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a certain number bits having a first logic state prior to storing the user data in memory cells. Subsequently, reading the encoded user data may be carried out by applying a read voltage to the memory cells while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. The auto-referenced read may identify a particular switching event that correlates to a median threshold voltage value of the subset of the memory cells. Then, the auto-referenced read may determine a reference voltage that takes into account a statistical property of threshold voltage distribution of the subset of the memory cells. The auto-referenced read may identify a time duration to maintain the read voltage based on determining the reference voltage. When the time duration expires, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.
1. A method, comprising:
applying a ramping voltage to a memory array to activate a group of memory cells storing encoded data of the memory array;
determining, at a first time, that a first set of memory cells storing encoded data has been switched to an active state based at least in part on applying the ramping voltage;
maintaining application of the ramping voltage for a duration after the first time, the duration based at least in part on the first set of memory cells being switched to the active state; and
determining, after an end of the duration, a logic state of a second set of memory cells storing encoded data that includes the first set of memory cells based at least in part on the second set of memory cells being switched to the active state.
2. The method of claim 1 , further comprising:
determining that the second set of memory cells corresponds to a first logic state.
3. The method of claim 1 , wherein:
the determination that the first set of memory cells has been switched to the active state is based at least in part on a median threshold voltage value of a subset of the group of memory cells, wherein threshold voltages of the subset of memory cells are less than threshold voltages of remaining memory cells of the group.
4. The method of claim 1 , wherein:
the duration is determined based at least in part on additional memory cells being switched to the active state, wherein the second set of memory cells comprises the first set of memory cells and the additional memory cells.
5. The method of claim 1 , wherein:
the ramping voltage has an initial value that is less than a smallest threshold voltage of a set of memory cells.
6. The method of claim 1 , wherein:
the ramping voltage has an initial value that is greater than a smallest threshold voltage of a set of memory cells and less than a median threshold voltage of the set of memory cells.
7. The method of claim 1 , wherein:
the ramping voltage has a constant rate of increase with respect to time.
8. The method of claim 1 , further comprising:
determining that a third set of memory cells corresponds to a second logic state different from a first logic state, wherein the third set of memory cells remain unswitched after the end of the duration.
9. An electronic memory apparatus, comprising:
a memory array; and
a controller in electronic communication with the memory array, wherein the controller is operable to:
apply a ramping voltage to the memory array to activate a group of memory cells storing encoded data of the memory array;
determine, at a first time, that a first set of memory cells storing encoded data has been switched to an active state based at least in part on applying the ramping voltage;
maintain application of the ramping voltage for a duration after the first time, the duration based at least in part on the first set of memory cells being switched to the active state; and
determine, after an end of the duration, a logic state of a second set of memory cells storing encoded data that includes the first set of memory cells based at least in part on the second set of memory cells being switched to the active state.
10. The electronic memory apparatus of claim 9 , wherein the controller is further operable to:
determine that the second set of memory cells corresponds to a first logic state.
11. The electronic memory apparatus of claim 9 , wherein the controller is further operable to:
determine that the first set of memory cells has been switched to the active state based at least in part on a median threshold voltage value of a subset of the group of memory cells, wherein threshold voltages of the subset of memory cells are less than threshold voltages of remaining memory cells of the group.