DOUBLE PATTERNING METHOD TO FORM SUB-LITHOGRAPHIC PILLARS
A method and resulting structure, is disclosed to fabricate vertical bipolar junction transistors including a regular array of base contact pillars and emitter contact pillars with a at least one dimension below the minimum lithographical resolution, F, of the lithographic technique employed. A storage element, such as a phase change storage element, can be formed above the regular array of base contact pillars and emitter contact pillars.
1 . A method of fabricating an electronic device, the method comprising:
forming an array of base contact pillars and an array of emitter contact pillars, the forming of the array of base contact pillars and the array of the emitter contact pillars including a double-patterning technique including
forming a first set of shallow trench isolation regions extending at least to a first doped region, and
forming a second set of shallow trench isolation regions which do not extend to the first doped region, the first doped region being a common collector, the second set of shallow trench isolation regions being formed substantially perpendicular to the first set of shallow trench isolation regions.
2 . The method of claim 1 , wherein the second set of shallow trench isolation regions extend to a second doped region, the second doped region having a polarity opposite that of the first doped region.
3 . The method of claim 1 , further comprising forming the base contact pillars and the emitter contact pillars to each have a width of about F/2, where F is a minimum lithographical resolution of a lithographic system used to form the electronic device.
4 . The method of claim 1 , wherein the double-patterning technique further includes:
partially removing a dielectric material from between a patterned etch stop layer after filling each set of shallow trench isolation regions with the dielectric material; and
removing the patterned etch stop layer after partially removing the dielectric material from between the patterned etch stop layer.
5 . The method of claim 1 , further comprising forming a storage element above the array of base contact pillars and the array of emitter contact pillars.
6 . The method of claim 5 , wherein the storage element is a phase change memory device.
7 . The method of claim 1 , wherein forming the array of base contact pillars and the array of emitter contact pillars comprises a first-patterning technique and a second-patterning technique, the second-patterning technique being in a direction about perpendicular to a direction of the first-patterning technique.
8 . The method of claim 7 , wherein the first-patterning technique includes:
forming a first-dielectric layer, a first etch-stop layer, and a first fin-patterning layer over a substrate;
lithographically patterning the fin patterning layer with an array of first strips having a width approximately equal to a minimum lithographical resolution F, where F is a minimum lithographical resolution of a lithographic system used to form the electronic device;
forming an array of first fins having a width of approximately F/2;
depositing a conformal layer over the fins, the conformal layer having a thickness of approximately F/2 on the sidewalls of the fins;
anisotropically etching the fins;
selectively removing the fins;
etching through the first etch-stop layer and the first-dielectric layer; and
etching into the substrate to form a first set of shallow-trench isolation regions which define first-direction active area strips, a patterned first-dielectric layer, and a patterned first etch-stop layer.
9 . The method of claim 1 , wherein the array of base contact pillars and the array of emitter contact pillars each have a pitch of about F, where F is a minimum lithographical resolution of a lithographic system used to form the electronic device.
10 . A method of fabricating an electronic device, the method comprising:
forming an array of base contact pillars and an array of emitter contact pillars, the forming of the array of base contact pillars and the array of the emitter contact pillars including a double-patterning technique including
forming a first set of shallow trench isolation regions extending at least to a first region, and
forming a second set of shallow trench isolation regions which do not extend to the first region, the second set of shallow trench isolation regions being formed substantially perpendicular to the first set of shallow trench isolation regions.
11 . The method of claim 10 , wherein the first region is a doped region and forms a common collector.
12 . The method of claim 10 , further comprising:
forming a dopant having a first polarity in the emitter contact pillars to form doped emitter contacts having the first polarity; and
forming a dopant of a second polarity in the base contact pillars to form doped base contacts having the second polarity.
13 . The method of claim 10 , further comprising forming a first level base contact plug in electrical contact with a number of base contact pillars.
14 . A method of forming vertical bipolar junction transistors, the method comprising:
forming a regular array of base contact pillars and a regular array of emitter contact pillars, the base contact pillars and the emitter contact pillars each having a width below a minimum lithographical resolution, F, where F is a minimum lithographical resolution of a lithographic system used to form the electronic device;
forming a first level base contact plug in electrical contact with a number of the base contact pillars; and
forming a storage element above the regular array of base contact pillars and the regular array of emitter contact pillars.
15 . The method of claim 14 , further comprising forming a number of word lines above the storage element.
16 . The method of claim 14 , further comprising:
forming a first set of shallow trench isolation regions extending at least to a first region, and
forming a second set of shallow trench isolation regions which do not extend to the first region, the first region being a common collector, the second set of shallow trench isolation regions being formed substantially perpendicular to the first set of shallow trench isolation regions.
17 . The method of claim 16 , further comprising doping the first region.
18 . The method of claim 14 , further comprising forming the regular array of base contact pillars and the regular array of emitter contact pillars to share a common collector.
19 . The method of claim 14 , further comprising defining the regular array of base contact pillars and the regular array of emitter contact pillars by forming a first set of substantially parallel trenches in a first direction and forming a second set of substantially parallel trenches in a second direction that is approximately perpendicular to the first direction.
20 . The method of claim 14 , further comprising separating each row of the emitter contact pillars from an adjacent row by forming a shallow trench isolation region therebetween.