IP Library Granted Patent US 10,431,739
Granted Patent B2
US 10,431,739 · App. 15/858,728 · Granted Oct 1, 2019

Clamp elements for phase change memory arrays

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Quick Facts
Patent No.
US 10,431,739
App. No.
15/858,728
Granted
Oct 1, 2019
Kind
B2
Abstract

Clamp elements, memories, apparatuses, and methods for forming the same are disclosed herein. An example memory may include an array of memory cells and a plurality of clamp elements. A clamp element of the plurality of clamp elements may include a cell structure formed non-orthogonally relative to at least one of a bit line or a word line of the array of memory cells and may be configured to control a voltage of a respective bit line.

Claims (23)

1. A method for forming cell structures, comprising:

forming a chalcogenic material over a plurality of contacts;

after forming the chalcogenic material, forming a mask material;

removing portions of the mask material to form a plurality of mask elements, wherein at least a mask hole is located between the plurality of mask elements and positioned non-orthogonally relative the plurality of contacts;

removing a portion of the chalcogenic material to form a plurality of chalcogenic material elements; and

forming a plurality of bit lines over the chalcogenic material elements.

2. The method of claim 1 , wherein the chalcogenic material comprises GST.

3. The method of claim 1 , further comprising:

forming a bit line cap material over the chalcogenic material.

4. The method of claim 1 , wherein said forming the plurality of bit lines comprises:

forming a bit line mask configured to provide a bit line pattern; and

removing exposed portions of the chalcogenic material between the bit line mask.

5. The method of claim 1 ; further comprising:

after forming the mask hole in the mask material, forming a spacer material.

6. The method of claim 1 , further comprising:

after forming the chalcogenic material, forming a bit line cap material over the chalcogenic material.

7. The method of claim 6 , further comprising:

forming a sealant material over the plurality of chalcogenic material elements.

8. The method of claim 7 , further comprising:

forming a filling material over the sealant material.

9. The method of claim 8 , further comprising:

removing at least a portion of the filling material and the sealant material to expose the bit line cap material.

10. The method of claim 9 , wherein the plurality of hit lines contact the exposed bit line cap material.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050716/0678 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 7 TO PATENT SECURITY AGREEMENT Recorded Feb 6, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 045267/0833 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 29, 2017
From: RIGANO, ANTONINO; PELLIZZER, FABIO
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044507/0806 →