Apparatuses and methods for concentrated arrangement of transistors of multiple amplifier circuits
Apparatuses and methods for concentrated arrangement of amplifiers. An example apparatus may include a first amplifier circuit including a first and second transistors. The first width different from the second width, the first length different from the second length. The apparatus further including a second amplifier circuit including a third and fourth transistors. The first transistor including a first gate electrode and the third transistor having a third gate electrode each having a first length and a first, diffusion region and a third diffusion region, respectively, each having a first width, and the second transistor including a second gate electrode and the fourth transistor having a fourth gate electrode each with a fourth length and a second diffusion region and a fourth diffusion region, respectively, each having a second width. The first and third transistors are collectively arranged and the second and fourth transistors are collectively arranged.
1. An apparatus comprising:
a first amplifier circuit comprising a first transistor and a second transistor, the first transistor comprising a first gate electrode having a first length and a first diffusion region having a first width, the second transistor comprising a second gate electrode having a second length and a second diffusion region having a second width, the first width different from the second width, the first length different from the second length;
a second amplifier circuit comprising a third transistor and a fourth transistor, the third transistor comprising a third gate electrode having the first length and a third diffusion region having the first width, the fourth transistor comprising a fourth gate electrode having a fourth length and a fourth diffusion region having the second width;
wherein the first and third transistors are collectively arranged and the second and fourth transistors are collectively arranged; and
a bias reference voltage generation circuit comprising a fifth transistor and a sixth transistor, the fifth transistor comprising a fifth gate electrode having the first length and a fifth diffusion region having the first width, the sixth transistor comprising a sixth gate electrode having a fourth length and a sixth diffusion region having the second width, wherein the fifth transistor is collectively arranged with the first and third transistors and the sixth transistor is collectively arranged with the second and fourth transistors.
2. The apparatus of claim 1 , wherein the first transistor and the third transistor are formed adjacent to each other such that the first diffusion region and the third diffusion region overlap.
3. The apparatus of claim 1 , wherein a dummy transistor is formed between the first transistor and the third transistor such that the first diffusion region is completely separate from the third diffusion region.
4. The apparatus of claim 1 , wherein the transistor group is formed in a single substrate well.
5. The apparatus of claim 1 , wherein the first, third, and fifth transistors collectively form a transistor group, the apparatus further comprising a dummy transistor formed on each end of the transistor group.
6. The apparatus of claim 1 , wherein the sixth transistor is formed between the first and third transistors.
7. The apparatus of claim 1 , wherein the bias signal generation circuit is configured to provide bias voltage signals to the first amplifier circuit and to the second amplifier circuit, wherein the first amplifier circuit is configured to provide a first output signal in response to first and second input signals having a voltage based on the bias voltage signals, and wherein the second amplifier circuit is configured to provide a second output signal in response to third and fourth input signals having a voltage based on the bias voltage signals.
8. An apparatus comprising:
a first amplifier circuit comprising a first transistor and a second transistor, the first transistor comprising a first gate electrode having a first length and a first diffusion region having a first width, the second transistor comprising a second gate electrode having a second length and a second diffusion region having a second width, the first width different from the second width, the first length different from the second length;
a second amplifier circuit comprising a third transistor and a fourth transistor, the third transistor comprising a third gate electrode having the first length and a third diffusion region having the first width, the fourth transistor comprising a fourth gate electrode having a fourth length and a fourth diffusion region having the second width;
a first well region formed on a semiconductor substrate and surrounded by an element isolation region;
a second well region formed on the semiconductor substrate and surrounded by the element isolation region,
wherein the first and third transistors are formed in the first well region,
wherein the second and fourth transistors are formed in the second well region; and
a bias signal generation circuit configured to provide a bias voltage signals to the first amplifier circuit and to the second amplifier circuit, wherein the first amplifier circuit is configured to provide first voltage reference signal in response to first and second input signals, and wherein the second amplifier circuit is configured to provide a second voltage reference signal in response to third and fourth input signals, wherein voltage levels of the first voltage reference signal and the second voltage reference signal are based on the bias voltage signals.
9. The apparatus of claim 8 , wherein, within the first well region, the first transistor and the third transistor are formed adjacent to each other such that the first diffusion region and the third diffusion region overlap.
10. The apparatus of claim 8 , wherein a dummy transistor is formed within the first well region between the first transistor and the third transistor.
11. The apparatus of claim 8 , wherein the first and third form at least part of a transistor group, wherein the apparatus further comprising a dummy transistor formed on each end of the transistor group.
12. The apparatus of claim 8 , further comprising a sixth transistor formed between the first and third transistors, wherein the sixth transistor is part of a bias signal generation circuit.
13. The apparatus of claim 12 , wherein the sixth transistor comprises a sixth gate electrode having the first length and a sixth diffusion region having the first width.