Memory systems and memory programming methods
Memory systems and memory programming methods are described. In one arrangement, a memory system includes a memory cell configured to have a plurality of different memory states, an access circuit coupled with the memory cell and configured to provide a first signal to a memory element of the memory cell to program the memory cell from a first memory state to a second memory state, and a current source coupled with the memory cell and configured to generate a second signal which is provided to the memory element of the memory cell after the first signal to complete programming of the memory cell from the first memory state to the second memory state.
1. A memory system comprising:
a memory element configured to be programmed to a plurality of different memory states at a plurality of different moments in time;
circuitry configured to implement a programming operation to change the programming of the memory element from a first of the memory states to a second of the memory states, and wherein the circuitry is configured to apply first and second programming signals within respective different current ranges to the memory element to implement the programming operation; and
wherein the circuitry is configured to apply the first programming signal to the memory element before the application of the second programming signal to the memory element.
2. The system of claim 1 wherein the memory element has an increased electrical resistance in the first memory state compared with the second memory state.
3. The system of claim 1 wherein the first programming signal is within an increased current range compared with the second programming signal.
4. The system of claim 1 wherein the application of the first programming signal forms an electrically conductive structure within dielectric material of the memory element, and the application of the second programming signal increases a number of ions of the electrically conductive structure within the memory element.
5. The system of claim 1 wherein the application of the first programming signal forms an electrically conductive structure within dielectric material of the memory element, and the application of the second programming signal increases a width of the electrically conductive structure within the memory element.
6. The system of claim 1 wherein the circuitry comprises:
a transistor configured to regulate the first programming signal; and
a current source configured to generate the second programming signal.
7. The system of claim 1 wherein the memory element is configured to change from the first memory state to the second memory state during the applying of the first programming signal to the memory element, and the memory element is configured to retain the second memory state after the applying of the second programming signal to the memory element.
8. The system of claim 1 wherein the circuitry is configured to regulate the second programming signal to have at least a substantially constant current.
9. The system of claim 1 wherein the second programming signal has increased current compared with the first programming signal.
10. A memory system comprising:
a memory element configured to be programmed to a plurality of different memory states at a plurality of different moments in time; and
circuitry configured to implement a programming operation to change the programming of the memory element from a first of the memory states to a second of the memory states, and wherein the circuitry is configured to implement the programming operation by applying a first programming signal to the memory element to change the memory element from the first memory state to the second memory state and applying a second programming signal to the memory element after the change of the memory element from the first memory state to the second memory state, wherein the first and second programming signals are controlled to have different electrical characteristics.
11. The system of claim 10 wherein the circuitry comprises a switching device coupled with the memory element, and wherein the circuitry is configured to provide a first bias signal to the switching device to control the application of the first programming signal to the memory element and a second bias signal to the switching device to control the application of the second programming signal to the memory element, wherein the second bias signal has an increased voltage potential compared with the first bias signal.
12. The system of claim 11 wherein the first bias signal regulates current of the first programming signal to be within a desired range.
13. The system of claim 10 wherein the memory element has an increased electrical resistance in the first memory state compared with the second memory state.
14. The system of claim 10 wherein the first programming signal is within an increased current range compared with the second programming signal.
15. The system of claim 10 wherein the application of the first programming signal forms an electrically conductive structure within dielectric material of the memory element, and the application of the second programming signal increases a number of ions of the electrically conductive structure within the memory element.
16. The system of claim 10 wherein the application of the first programming signal forms an electrically conductive structure within dielectric material of the memory element, and the application of the second programming signal increases a width of the electrically conductive structure within the memory element.
17. The system of claim 10 wherein the circuitry comprises:
a transistor configured to regulate the first programming signal; and
a current source configured to generate the second programming signal.
18. The system of claim 10 wherein the memory element is configured to change from the first memory state to the second memory state during the applying of the first programming signal to the memory element, and the memory element is configured to retain the second memory state after the applying of the second programming signal to the memory element.
19. The system of claim 10 wherein the circuitry is configured to regulate the second programming signal to have at least a substantially constant current.
20. The system of claim 10 wherein the second programming signal has increased current compared with the first programming signal.
21. A memory programming method comprising:
using a bit line, applying a voltage potential across a memory element to initiate a programming operation to change the programming of the memory element from a first memory state to a second memory state;
changing the memory element from the first memory state to the second memory state during the applying;
after the applying, discharging the bit line while the memory element is in the second memory state; and
using the bit line, conducting a current from a current source to the memory element in the second memory state after the discharging to complete the programming operation.
22. The method of claim 21 wherein the memory element has an increased electrical resistance in the first memory state compared with the second memory state.
23. The method of claim 21 wherein the current is a first current, a second current is conducted via the bit line during the applying, and the second current is within an increased current range compared with the first current.
24. The method of claim 21 wherein the applying forms an electrically conductive structure within dielectric material of the memory element, and the conducting increases a number of ions of the electrically conductive structure within the memory element.
25. The method of claim 21 wherein the applying forms an electrically conductive structure within dielectric material of the memory element, and the conducting increases a width of the electrically conductive structure within the memory element.
26. The method of claim 21 wherein the current is a first current, and further comprising regulating a second current conducted via the bit line during the applying.
27. The method of claim 26 wherein the first current is larger than the second current.
28. The method of claim 21 wherein the applying comprises applying using a selector transistor coupled with the bit line.
29. The method of claim 21 wherein the memory element is configured to change from the first memory state to the second memory state during the applying, and the memory element is configured to retain the second memory state after the conducting.
30. The method of claim 21 further comprising regulating the current to be at least substantially constant during the conducting.