Transistors, memory cells and semiconductor constructions comprising ferroelectric gate dielectric
Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.
1. A semiconductor construction, comprising:
a semiconductor base having a recess extending into a conductively doped region of the semiconductor base through an upper surface, the conductively doped region being doped with a first-type dopant;
a source region within the semiconductor base on a first side of the recess and a drain region within the semiconductor base on a second side of the recess, the source region and the drain region being majority conductively doped with a second-type dopant, the first-type and second-type dopants being opposite dopant types relative to each other;
a gate material comprising a metal material disposed within the recess between the source region and the drain region, the gate material having a top surface elevationally equivalent with the upper surface of the semiconductor base and a lower surface within the conductively doped region of the semiconductor base;
a non-ferroelectric dielectric material disposed between the source region and the gate material and between the drain region and the gate material, the non-ferroelectric dielectric material being in direct physical contact with the semiconductor base along the source region and the drain region within the recess; and
a ferroelectric material between the non-ferroelectric dielectric material and the gate material along the source region and the drain region, the ferroelectric material being in direct physical contact with the metal material of the gate and comprising one or more materials selected from the group consisting of yttrium-doped zirconium oxide, yttrium-doped hafnium oxide, magnesium-doped hafnium oxide, magnesium-doped zirconium oxide, silicon-doped zirconium oxide, and silicon-doped hafnium oxide.
2. The semiconductor construction of claim 1 wherein the ferroelectric material is in direct physical contact with the non-ferroelectric dielectric material.
3. The semiconductor construction of claim 1 wherein the ferroelectric material is in direct physical contact with the gate material.
4. The semiconductor construction of claim 1 wherein the non-ferroelectric dielectric material comprises Si, O and N.
5. The semiconductor construction of claim 1 wherein the ferroelectric material comprises one or more of Hf, Zr, Si, O, Y, Ba, Mg and Ti.
6. The semiconductor construction of claim 1 wherein the ferroelectric material comprises hafnium oxide.
7. The semiconductor construction of claim 1 wherein the non-ferroelectric dielectric material lines an entirety of the semiconductor base within the recess, along a cross section.
8. The semiconductor construction of claim 7 wherein the non-ferroelectric dielectric material has an outer surface contacting the semiconductor base and an opposing inner surface, and wherein the ferroelectric material is present along an entirety of the inner surface along the cross section.
9. The semiconductor construction of claim 1 wherein an entirety of the gate material is within the recess and does not extend above the upper surface.
10. A transistor, comprising:
a recessed gate having an upper surface coplanar with an upper surface of a substrate, the recessed gate comprising a metal material;
a p-type doped source region;
a p-type doped drain region; and
a gate dielectric between the recessed gate and the p-type doped source and drain regions; the gate dielectric comprising a non-ferroelectric material and a ferroelectric material between the p-type doped source region and the recessed gate, the ferroelectric material comprising one or more materials selected from the group consisting of yttrium-doped zirconium oxide, yttrium-doped hafnium oxide, magnesium-doped hafnium oxide, magnesium-doped zirconium oxide, silicon-doped zirconium oxide, and silicon-doped hafnium oxide, the recessed gate extending into an n-type doped region of the substrate and being in direct physical contact with the ferroelectric material.
11. The transistor of claim 10 wherein the gate dielectric further comprises the non-ferroelectric material and the ferroelectric material between the p-type doped drain region and the recessed gate.
12. The transistor of claim 10 wherein the ferroelectric material comprises one or more of Hf, Zr, Si, O, Y, Ba, Mg and Ti.
13. The transistor of claim 10 wherein the ferroelectric material comprises hafnium oxide.
14. The transistor of claim 10 wherein the non-ferroelectric material comprises Si, O and N.
15. The transistor of claim 10 wherein the recessed gate is disposed within a recess in a semiconductive material and wherein the gate dielectric lines an entirety of the recess along a cross section.
16. The transistor of claim 15 wherein the gate dielectric is in direct physical contact with the semiconductive material.
17. A transistor, comprising:
a recessed gate comprising a metal material having an upper surface coplanar with an upper surface of a substrate;
an n-type doped source region;
an n-type doped drain region; and
a gate dielectric between the recessed n-type doped gate and the source and drain regions; the gate dielectric comprising a non-ferroelectric material and a ferroelectric material between the n-type doped source region and the recessed gate, the ferroelectric material comprising one or more materials selected from the group consisting of yttrium-dopes zirconium oxide, yttrium-doped hafnium oxide, magnesium-doped hafnium oxide, magensium-doped zirconium oxide, silicon-doped zirconium oxide, and silicon-doped hafnium oxide, the recessed gate extending into a p-type doped region of the substrate and being in direct physical contact with the ferroelectric material.