Transistors, memory cells and semiconductor constructions
View Patent ↗Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.
1. A semiconductor construction, comprising:
a dielectric region configured as an upwardly-opening structure;
a gate extending into the upwardly-opening structure; a source region being adjacent one side of the gate and a drain region being adjacent another side of the gate; the source region being spaced from the gate by a first segment of the dielectric region, and the drain region being spaced from the gate by a second segment of the dielectric region; a third segment of the dielectric region being a bottom of the upwardly-opening structure and being between the first and second segments;
wherein a portion of the dielectric region comprises a non-ferroelectric material as an outer boundary, and comprises a ferroelectric material between the non-ferroelectric material and the gate; and
wherein the ferroelectric material is only within the first segment.
2. The semiconductor construction of claim 1 wherein the dielectric region is thicker along the third segment than along the first and second segments.
3. The semiconductor construction of claim 1 wherein the non-ferroelectric material comprises one or both of silicon dioxide and silicon nitride.
4. The semiconductor construction of claim 1 further comprising a capacitor coupled to the drain region.
5. The semiconductor construction of claim 1 wherein the ferroelectric material comprises one or more of Hf, Zr, Si, O, Y, Ba, Mg and Ti.
6. The semiconductor construction of claim 1 wherein the non-ferroelectric material comprises a thickness within the first and second segments within a range of from about 10 angstroms to about 20 angstroms, and comprises a thickness within the third segment within a range of from about 25 angstroms to about 50 angstroms.
7. A transistor, comprising:
a first dielectric region between a gate and a source region;
a second dielectric region between the gate and a drain region;
the first dielectric region comprising two materials; one of the two materials being ferroelectric material and another of the two materials being a first non-ferroelectric material;
the second dielectric region comprising only a single material, said single material being a second non-ferroelectric material; and
wherein the first and second non-ferroelectric materials are different compositions relative to one another.
8. The transistor of claim 7 wherein the ferroelectric material comprises one or more of Hf, Zr, Si, O, Y, Ba, Mg and Ti.
9. The transistor of claim 7 wherein the source and drain regions are conductively-doped regions of a semiconductor material.
10. The transistor of claim 9 wherein the source region comprises a dopant gradient.
11. A transistor, comprising:
a first dielectric region between a gate and a source region;
a second dielectric region between the gate and a drain region;
the first dielectric region comprising two materials; one of the two materials being ferroelectric material and another of the two materials being a first non-ferroelectric material;
the second dielectric region comprising only a single material, said single material being a second non-ferroelectric material;
wherein the source and drain regions are conductively-doped regions of a semiconductor material; and
wherein an entirety of the drain region is more heavily doped than any of the source region.