Patent Assignment
Reel/Frame 050702/0451
Release of Security Interest
Recorded: 2019-10-09
Pages: 24
Assignor
MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Executed: 2019-07-31
Assignee
MICRON TECHNOLOGY, INC.
8000 S FEDERAL WAY, BOISE, IDAHO, 83707
Covered Properties
(251)
Methods Using Block Copolymer Self-Assembly for Sub-Lithographic Patterning
PCT:
PCT/US2008/052022 ↗
Constructions Comprising Stacked Memory Arrays
PCT:
PCT/US2015/067264 ↗
Apparatuses and Methods for Scatter and Gather
PCT:
PCT/US2016/015027 ↗
Apparatuses and Methods for Parallel Writing to Multiple Memory Device Locations
PCT:
PCT/US2016/015029 ↗
Methods of Forming a Magnetic Electrode of a Magnetic Tunnel Junction and Methods of Forming a Magnetic Tunnel Junction
PCT:
PCT/US2016/018045 ↗
Data Shift by Elements of a Vector in Memory
PCT:
PCT/US2016/021359 ↗
Magnetic Tunnel Junctions
PCT:
PCT/US2016/024219 ↗
Virtual Register File
PCT:
PCT/US2016/025499 ↗
Array of Cross Point Memory Cells
PCT:
PCT/US2016/040131 ↗
Cell-Based Reference Voltage Generation
PCT:
PCT/US2017/014922 ↗
Distributed Input/Output Virtualization
PCT:
PCT/US2017/015585 ↗
Error Rate Reduction
PCT:
PCT/US2017/015944 ↗
Apparatuses and Methods for Partitioned Parallel Data Movement
PCT:
PCT/US2017/016186 ↗
Data Gathering in Memory
PCT:
PCT/US2017/016425 ↗
Apparatuses and Methods for Internal Heat Spreading for Packaged Semiconductor Die
PCT:
PCT/US2017/016941 ↗
Apparatuses and Methods for Multiple Address Registers for a Solid State Device
PCT:
PCT/US2017/017170 ↗
Apparatuses and Methods for Photonic Communication and Photonic Addressing
PCT:
PCT/US2017/017460 ↗
Apparatuses and Methods for Data Movement
PCT:
PCT/US2017/017613 ↗
Modified Decode for Corner Turn
PCT:
PCT/US2017/017760 ↗
Selectors on Interface Die for Memory Device
PCT:
PCT/US2017/017892 ↗
Data Transfer with a Bit Vector Operation Device
PCT:
PCT/US2017/017919 ↗
Redundant Array of Independent Nand for a Three-Dimensional Memory Array
PCT:
PCT/US2017/018252 ↗
Low Capacitance Through Substrate via Structures
PCT:
PCT/US2017/018834 ↗
Ground Reference Scheme for a Memory Cell
PCT:
PCT/US2017/020251 ↗
Apparatuses and Methods for Logic/Memory Devices
PCT:
PCT/US2017/020394 ↗
Conductive Structures, Systems and Devices Including Conductive Structures and Related Methods
PCT:
PCT/US2017/020456 ↗
Memory Cell Sensing with Storage Component Isolation
PCT:
PCT/US2017/020687 ↗
Magnetic Tunnel Junctions
PCT:
PCT/US2017/020734 ↗
Apparatuses and Methods for Cache Invalidate
PCT:
PCT/US2017/021041 ↗
Memory Devices Including Dynamic Superblocks, and Related Methods and Electronic Systems
PCT:
PCT/US2017/021071 ↗
Parallel Access Techniques Within Memory Sections Through Section Independence
PCT:
PCT/US2017/021199 ↗
Apparatuses and Methods for Operations Using Compressed and Decompressed Data
PCT:
PCT/US2017/021758 ↗
Offset Compensation for Ferroelectric Memory Cell Sensing
PCT:
PCT/US2017/021884 ↗
Refresh Circuitry
PCT:
PCT/US2017/022047 ↗
Apparatuses and Methods for a Load Current Control Circuit for a Source Follower Voltage Regulator
PCT:
PCT/US2017/022245 ↗
Folding Device Stand for Portable Devices
PCT:
PCT/US2017/022286 ↗
Feram-Dram Hybrid Memory
PCT:
PCT/US2017/022677 ↗
Ferroelectric Memory Cell Sensing
PCT:
PCT/US2017/022678 ↗
Monitoring Error Correction Operations Performed in Memory
PCT:
PCT/US2017/022897 ↗
Thermal Insulation for Three-Dimensional Memory Arrays
PCT:
PCT/US2017/022984 ↗
Apparatuses and Methods for Cache Operations
PCT:
PCT/US2017/023159 ↗
Apparatuses and Methods for Data Movement
PCT:
PCT/US2017/023162 ↗
Apparatuses and Methods for Automated Dynamic Word Line Start Voltage
PCT:
PCT/US2017/023402 ↗
Apparatuses and Methods for Controlling Wordlines and Sense Amplifiers
PCT:
PCT/US2017/023548 ↗
Methods and Apparatuses Including Command Delay Adjustment Circuit
PCT:
PCT/US2017/023594 ↗
Charge Extraction from Ferroelectric Memory Cell
PCT:
PCT/US2017/023907 ↗
Memory Device with Direct Read Access
PCT:
PCT/US2017/024790 ↗
Assemblies Having Shield Lines of an Upper Wiring Level Electrically Coupled with Shield Lines of a Lower Wiring Level
PCT:
PCT/US2017/024835 ↗
Error Correction Code (Ecc) Operations in Memory
PCT:
PCT/US2017/025688 ↗
Charge Sharing Between Memory Cell Plates
PCT:
PCT/US2017/027952 ↗
Memory Arrays, Ferroelectric Transistors, and Methods of Reading and Writing Relative to Memory Cells of Memory Arrays
PCT:
PCT/US2017/027987 ↗
Integrated Structures Including Material Containing Silicon, Nitrogen, and at Least One of Carbon, Oxygen, Boron and Phosphorus
PCT:
PCT/US2017/027995 ↗
Memory Access Techniques in Memory Devices with Multiple Partitions
PCT:
PCT/US2017/028177 ↗
Method for Fabricating Semiconductor Components with Through Wire Interconnects
Microelectronic Devices and Methods for Manufacturing Microelectronic Devices
Application:
14/860,419 →
Publication:
US 2016/0031707
Discontinuous Patterned Bonds for Semiconductor Devices and Associated Systems and Methods
Interconnect Structure with Redundant Electrical Connectors and Associated Systems and Methods
Method, Apparatus and System Providing a Storage Gate Pixel with High Dynamic Range
Back-To-Back Solid State Lighting Devices and Associated Methods
System and Method for Controlling User Access to an Electronic Device
Pixel with Strained Silicon Layer for Improving Carrier Mobility and Blue Response in Imagers
Solid State Transducers with State Detection, and Associated Systems and Methods
Semiconductor Die Assemblies Having Molded Underfill Structures and Related Technology
Apparatus Providing Simplified Alignment of Optical Fiber in Photonic Integrated Circuits
Packaged Microelectronic Devices and Methods for Manufacturing Packaged Microelectronic Devices
Self-Measuring Nonvolatile Memory Device Systems and Methods
Solid State Lighting Device with Different Illumination Parameters at Different Regions of an Emitter Array
Memory Device Including Mixed Non-Volatile Memory Cell Types
Memory Including Blocking Dielectric in Etch Stop Tier
Transistors, Memory Cells and Semiconductor Constructions
Interconnect Systems and Methods Using Hybrid Memory Cube Links to Send Packetized Data Over Different Endpoints of a Data Handling Device
Self-Aligned Cross-Point Phase Change Memory-Switch Array
Memory Devices Having Differently Configured Blocks of Memory Cells
Setting a Default Read Signal Based on Error Correction
Semiconductor Device with Modified Current Distribution
Fixed Voltage Sensing in a Memory Device
Frequency Synthesis for Memory Input-Output Operations
Memory Device Including Multiple Gate-Induced Drain Leakage Current Generator Circuits
Patent:
9,916,901 →
Application:
15/416,870 →
Method for Controlling User Access to an Electronic Device
Forming Conductive Plugs for Memory Device
Patent:
9,997,452 →
Application:
15/418,568 →
Methods and Apparatuses for Differential Signal Termination
Apparatuses and Methods for Distributing Row Hammer Refresh Events Across a Memory Device
Integrated Structures and Nand Memory Arrays
Microelectronic Device Packages, Stacked Microelectronic Device Packages, and Methods for Manufacturing Microelectronic Devices
Memory Arrays and Methods of Forming Memory Arrays
Proximity Coupling of Interconnect Packaging Systems and Methods
Nand Memory Arrays
Memory Arrays, and Methods of Forming Memory Arrays
Multi-Bit Ferroelectric Memory Device and Methods of Forming the Same
Memory Cell Structures
Interconnect Structures with Intermetallic Palladium Joints and Associated Systems and Methods
Methods and Systems for Imaging and Cutting Semiconductor Wafers and Other Semiconductor Workpieces
Pre-Writing Memory Cells of an Array
Vertical Solid-State Transducers Having Backside Terminals and Associated Systems and Methods
Methods Of Forming A Semiconductor Device Comprising First And Second Nitride Layers
Kvs Tree
Merge Tree Garbage Metrics
Merge Tree Modifications for Maintenance Operations
Stream Selection for Multi-Stream Storage Devices
Apparatuses and Methods for Controlling Wordlines and Sense Amplifiers
Recessed Transistors Containing Ferroelectric Material
Apparatuses and Methods for Providing Set and Reset Voltages at the Same Time
Apparatus Having Dice to Perorm Refresh Operations
Asymmetric Chip-to-Chip Interconnect
Phase Interpolators and Push-Pull Buffers
Controller to Manage Nand Memories
Memory Devices with Controllers Under Memory Packages and Associated Systems and Methods
Storage Devices Configured to Generate Linked Lists
Input Buffer Circuit
Patent:
9,911,471 →
Application:
15/432,864 →
Memory Cell Architecture for Multilevel Cell Programming
Error Correction Methods and Apparatuses Using First and Second Decoders
Efficient Utilization of Memory Die Area
Active Boundary Quilt Architecture Memory
Patent:
9,792,958 →
Application:
15/434,401 →
Solid State Drive Controller
Providing Power Availability Information to Memory
Refresh Address Controlling Scheme Based on Refresh Counter and Mask Circuit
Apparatuses and Methods for Reducing Read Disturb
Systems, Circuits, and Methods for Charge Sharing
Apparatuses and Methods for Pre-Fetching and Write-Back for a Segmented Cache Memory
Apparatuses and Methods Including Memory Access in Cross Point Memory
Programming Memory Cells to Be Programmed to Different Levels to an Intermediate Level from a Lowest Level
Memory Array Page Table Walk
Memory Apparatus with Post Package Repair
Patent:
9,805,828 →
Application:
15/438,459 →
Writing to Cross-Point Non-Volatile Memory
Systems and Methods for Reordering Packet Transmissions in a Scalable Memory System Protocol
Stacked Semiconductor Die Assemblies with Die Substrate Extensions
Apparatuses and Methods for Compute in Data Path
Semiconductor Constructions Which Include Metal-Containing Gate Portions and Semiconductor-Containing Gate Portions
Apparatuses Including Multiple Read Modes and Methods for Same
Apparatuses and Methods for in-Memory Operations
Low Capacitance Interconnect Structures and Associated Systems and Methods
Apparatuses and Methods for Performing Logical Operations Using Sensing Circuitry
Methods of Forming Metal on Inhomogeneous Surfaces and Structures Incorporating Metal on Inhomogeneous Surfaces
Programming a Memory Device in Response to Its Program History
Methods and Apparatus for Generation of Voltages
Loop Structure for Operations in Memory
Self-Reference for Ferroelectric Memory
Semiconductor Device Assemblies with Electrically Functional Heat Transfer Structures
Apparatuses and Methods for Sharing Transmission Vias for Memory Devices
Patent:
10,002,647 →
Application:
15/442,501 →
Apparatus for Impedance Adjustment and Methods of Their Operation
Threshold Voltage Distribution Determination by Sensing Common Source Line Currents
Apparatuses and Methods for Providing Internal Memory Commands and Control Signals in Semiconductor Memories
Apparatuses and Methods for Determining a Phase Relationship Between an Input Clock Signal and a Multiphase Clock Signal
Methods of Processing Wafer-Level Assemblies to Reduce Warpage, and Related Assemblies
Wireless Devices and Systems Including Examples of Configuration Modes for Baseband Units and Remote Radio Heads
Wireless Devices and Systems Including Examples of Full Duplex Transmission
Obfuscation-Enhanced Memory Encryption
Methods and Apparatuses for Processing Multiple Communications Signals with a Single Integrated Circuit Chip
Methods and Apparatuses for Determining Real-Time Location Information of Rfid Devices
Pre-Compensation of Memory Threshold Voltage
Apparatuses and Methods for Providing an Indicator of Operational Readiness of Various Circuits of a Semiconductor Device Following Power Up
Stack Refresh Control for Memory Device
Patent:
10,020,046 →
Application:
15/449,688 →
Memory Device Including Pass Transistors in Memory Tiers
Memory Having a Continuous Channel
Reducing Programming Disturbance in Memory Devices
Integrated Structures, Capacitors and Methods of Forming Capacitors
Methods of Forming Semiconductor Device Structures Including Linear Structures Substantially Aligned with Other Structures
Apparatuses and Methods for Charging a Global Access Line Prior to Accessing a Memory
Methods and Apparatuses for Compensating for Source Voltage
Conductive Components and Memory Assemblies
Patent:
9,773,807 →
Application:
15/455,859 →
Memory Device Command Receiving and Decoding Methods
Methods for Mitigating Power Loss Events During Operation of Memory Devices and Memory Devices Employing the Same
Application:
15/456,175 →
Publication:
US 2018/0261281
Assemblies Having Shield Lines of an Upper Wiring Layer Electrically Coupled with Shield Lines of a Lower Wiring Layer
Data Shift by Elements of a Vector in Memory
Memory Array Having Connections Going Through Control Gates
Folding Device Stand for Portable Devices
Memory Cells and Integrated Structures
Patent:
9,978,772 →
Application:
15/458,572 →
Methods of Forming a Ferroelectric Memory Cell
Semiconductor Memory Device Including Output Buffer
Solid State Memory Formatting with Padding Between Portions of System Data
Application:
15/460,296 →
Publication:
US 2017/0199702
Error Correction Code (Ecc) Operations in Memory for Providing Redundant Error Correction
Tiered Error Correction Code (Ecc) Operations in Memory
Methods for Forming Narrow Vertical Pillars and Integrated Circuit Devices Having the Same
Memory Tile Access and Selection Patterns
Apparatuses and Methods for Partial Bit De-Emphasis
Patent:
9,948,300 →
Application:
15/464,012 →
Semiconductor-Metal-On-Insulator Structures, Methods of Forming Such Structures, and Semiconductor Devices Including Such Structures
Packaged Leds with Phosphor Films, and Associated Systems and Methods
Timing Control for Input Receiver
Patent:
9,984,740 →
Application:
15/464,907 →
Apparatuses and Methods for in-Memory Data Switching Networks
Methods and Apparatuses for Signal Translation in a Buffered Memory
Transistors Having Strained Channel Under Gate in a Recess
Apparatuses and Methods for Operating Neural Networks
Apparatus and Methods for in Data Path Compute Operations
Chalcogenide Memory Device Components and Composition
Patent:
10,163,977 →
Application:
15/466,689 →
Vertical Memory Strings, and Vertically-Stacked Structures
Semiconductor Devices with Magnetic Regions and Attracter Material and Methods of Fabrication
Semiconductor Layered Device with Data Bus
Memory Protection Based on System State
Multiple Plate Line Architecture for Multideck Memory Array
Apparatuses and Methods for Current Limitation in Threshold Switching Memories
Apparatuses and Methods for in-Memory Operations
Patent:
10,049,721 →
Application:
15/470,516 →
Chained Bus Memory Device
Devices and Methods Including an Etch Stop Protection Material
Apparatuses and Methods for Configuring I/Os of Memory for Hybrid Memory Modules
Forming Array Contacts in Semiconductor Memories
Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells
Method of Forming Vias Using Silicon on Insulator Substrate
Selective Error Rate Information for Multidimensional Memory
Structures Incorporating and Methods of Forming Metal Lines Including Carbon
Apparatuses, Circuits, and Methods for Biasing Signal Lines
Ultrathin Solid State Dies and Methods of Manufacturing the Same
Microelectronic Die Packages with Metal Leads, Including Metal Leads for Stacked Die Packages, and Associated Systems and Methods
Recovery for Non-Volatile Memory After Power Loss
Methods for Forming Interconnect Assemblies with Probed Bond Pads
Memory Devices That Apply a Programming Potential to a Memory Cell in a String Coupled to a Source and Data Line Concurrently with Biasing the Data Line to a Greater Potential Than the Source
Garbage Collection
Operation of Mixed Mode Blocks
Memory Cell with Independently-Sized Elements
Functional Data Programming in a Non-Volatile Memory
Replacement Materials Processes for Forming Cross Point Memory
Semiconductor Devices Including a Diode Structure Over a Conductive Strap and Methods of Forming Such Semiconductor Devices
Semiconductor Device Assemblies with Molded Support Substrates
Three Dimensional Memory Array
Method and Apparatus for Reducing Impact of Transistor Random Mismatch in Circuits
Methods of Bit-Flagged Sketch-Based Memory Management and Memory Devices Utilizing the Same
Methods of Sketch-Based Memory Management and Memory Devices Utilizing the Same
Memory Management
Memory Systems and Methods Including Training, Data Organizing, and/or Shadowing
Methods and Apparatus Having Multiple Select Gates of Different Ranges of Threshold Voltages Connected in Series with Memory Cells
Patent:
10,014,061 →
Application:
15/484,369 →
Transaction Identification
Memory Protocol with Programmable Buffer and Cache Size
Application:
15/484,793 →
Publication:
US 2018/0292991
Apparatuses and Methods for Voltage Level Control
Scalable Low-Latency Storage Interface
Methods of Forming Phase Change Memory Apparatuses
Apparatuses and Methods for Controlling Wordlines and Sense Amplifiers
Patent:
10,020,038 →
Application:
15/488,328 →
Memories Having a Shared Resistance Variable Material
Erasable Block Segmentation for Memory
Construction of Integrated Circuitry and a Method of Forming an Elevationally-Extending Conductor Laterally Between a Pair of Structures
Element Value Comparison in Memory
Memory Device for a Hierarchical Memory Architecture
Signed Element Compare in Memory
Patent:
10,043,570 →
Application:
15/489,442 →
Data Storage with Data Randomizer in Multiple Operating Modes
Methods and Apparatuses for Modulating Threshold Voltages of Memory Cells
System and Method of Command Based and Current Limit Controlled Memory Device Power Up
Apparatuses and Methods for Forming Die Stacks
Device Having Multiple Channels with Calibration Circuit Shared by Multiple Channels
Solid-State Radiation Transducer Devices Having Flip-Chip Mounted Solid-State Radiation Transducers and Associated Systems and Methods
Progressive Effort Decoder Architecture
Semiconductor Device Including a Roll Call Circuit for Outputting Addresses of Defective Memory Cells
Memory Devices and Methods Which May Facilitate Tensor Memory Access with Memory Maps Based on Memory Operations
Apparatus and Method to Switch Configurable Logic Units
Apparatuses and Methods for Flexible Fuse Transmission
Patent:
9,824,770 →
Application:
15/493,772 →
Semiconductor Device with Single Ended Main I/O Line
Elevationally-Extending String Of Memory Cells And Methods Of Forming An Elevationally-Extending String Of Memory Cells
Apparatuses and Methods for Providing Word Line Voltages
Erasing Memory Cells
Memory Protocol
Application:
62/346,201 →
Memory Protocol with Command Priority
Application:
62/449,689 →
Integrated Memory Assemblies Comprising Multiple Memory Array Decks
Application:
62/452,193 →
Memory Device Loopback Systems and Methods
Application:
62/482,052 →
Memory Cells and Memory Arrays
Application:
62/488,232 →
Related Assignments
(3)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Mar 17, 2017
From: HOEM, SOPHIA; BREWER, WESLEY G.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 041608/0941 →
Assignment of Assignor's Interest
Mar 29, 2017
From: SZUBBOCSEV, ZOLTAN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 042113/0585 →
Release of Security Interest
Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →