IP Library Granted Patent US 10,050,084
Granted Patent B2
US 10,050,084 · App. 15/481,208 · Granted Aug 14, 2018

Replacement materials processes for forming cross point memory

Inventors: Jong-Won Lee (Boise, ID); Gianpaolo Spadini (Los Gatos, CA); Stephen W. Russell (Boise, ID); Derchang Kau (Cupertino, CA)
Assignee: MICRON TECHNOLOGY, INC.
H01L27/2463G11C13/004G11C13/0004G11C13/0023G11C13/0069G11C13/0097H01L27/24H01L27/2427H01L45/06H01L45/1233H01L45/1246H01L45/1253H01L45/141H01L45/142H01L45/143H01L45/144H01L45/1675H01L45/1683
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Quick Facts
Patent No.
US 10,050,084
App. No.
15/481,208
Granted
Aug 14, 2018
Kind
B2
Abstract

Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material.

Claims (35)

1. A method, comprising:

forming a first line stack oriented in a first direction, the first line stack including a chalcogenide line and at least one of a memory element of a memory cell or a selector element of the memory cell, or both; and

forming a second line stack oriented in a second direction different from the first direction, wherein forming the second line stack comprises forming a sacrificial line oriented in the second direction.

2. The method of claim 1 , wherein the first line stack comprises a first conductive line positioned below a first chalcogenide line.

3. The method of claim 1 , wherein the first line stack is positioned below the second line stack.

4. The method of claim 1 , further comprising:

removing sacrificial material of the sacrificial line; and

replacing the removed sacrificial material with a conductive material.

5. The method of claim 4 , further comprising:

depositing a dielectric material between a plurality of spaced-apart lines that extend in the second direction, wherein the plurality of spaced-apart lines comprise the conductive material.

6. The method of claim 5 , further comprising:

exposing alternating lines of the dielectric material and the conductive material.

7. The method of claim 1 , wherein a conductive material is positioned above a chalcogenide line of the second line stack.

8. The method of claim 1 , wherein forming the second line stack comprises:

forming a stack of materials that comprises a sacrificial material positioned above a chalcogenide material.

9. The method of claim 8 , wherein the stack of materials comprises the sacrificial material positioned above an electrode material.

10. An apparatus, comprising:

a first line stack oriented in a first direction, the first line stack including a memory element, or a selector element, or both of a memory cell; and

a second line stack oriented in a second direction different from the first direction, the second line stack including a chalcogenide line and an electrode line.

11. The apparatus of claim 10 , wherein the first line stack comprises a first conductive line and a first chalcogenide line.

12. The apparatus of claim 10 , wherein the second line stack comprises a conductive material.

13. The apparatus of claim 12 , wherein the conductive material is positioned above the chalcogenide line of the second line stack.

14. The apparatus of claim 12 , wherein the conductive material is included in the second line stack based at least in part on removing a portion of a sacrificial line of the second line stack.

15. The apparatus of claim 10 , wherein a stack of materials is positioned above a chalcogenide material of the second line stack.

16. The apparatus of claim 15 , wherein the stack of materials includes a conductive material positioned above an electrode material.

17. A method, comprising:

forming a first line stack oriented in a first direction;

forming a second line stack oriented in a second direction different from the first direction, forming the second line stack including forming a chalcogenide line and a sacrificial line; and

replacing a sacrificial material of the first line stack with a stack of materials that comprises a first chalcogenide material.

18. The method of claim 17 , further comprising:

forming a chalcogenide line extending in the first direction, the chalcogenide line comprising a memory element of a memory cell, or a selector element of the memory cell, or both.

19. The method of claim 18 , wherein forming the chalcogenide line comprises:

removing the sacrificial line; and

replacing a removed material of the sacrificial line with chalcogenide material.

20. The method of claim 17 , wherein the first line stack comprises a first conductive line positioned below the sacrificial line.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050702/0451 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 4 TO PATENT SECURITY AGREEMENT Recorded May 4, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042405/0909 →
Continuity (3)
Continuation 15058810 · Mar 2, 2016
Continuation 14228104 · Mar 27, 2014
Related Publication 20170263684A1 · Sep 14, 2017