IP Library Granted Patent US 9,659,997
Granted Patent B2
US 9,659,997 · App. 15/058,810 · Granted May 23, 2017

Replacement materials processes for forming cross point memory

Inventors: Jong-Won Lee (Boise, ID); Gianpaolo Spadini (Los Gatos, CA); Stephen W. Russell (Boise, ID); Derchang Kau (Cupertino, CA)
Assignee: MICRON TECHNOLOGY, INC.
H01L27/2463G11C13/004G11C13/0004G11C13/0023G11C13/0069G11C13/0097H01L27/24H01L27/2427H01L45/06H01L45/1233H01L45/1246H01L45/1253H01L45/141H01L45/142H01L45/143H01L45/144H01L45/1675H01L45/1683
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Quick Facts
Patent No.
US 9,659,997
App. No.
15/058,810
Granted
May 23, 2017
Kind
B2
Abstract

Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material.

Claims (50)

1. A method, comprising:

forming a first line stack oriented in a first direction, the first line stack including a first chalcogenide line over a first conductive line, wherein the first chalcogenide line is a memory element or a selector element of a memory cell; and

forming a second line stack oriented in a second direction different from the first direction, the second line stack positioned above the first line stack and including a sacrificial line.

2. The method of claim 1 , further comprising:

forming a conductive line oriented in the second direction, wherein forming the conductive line comprises:

removing sacrificial material of the sacrificial line, and

replacing the removed sacrificial material.

3. The method of claim 1 , wherein a second chalcogenide line is positioned below the sacrificial line of the second line stack.

4. The method of claim 1 , wherein forming the second line stack comprises:

forming a stack of material that includes a sacrificial material; and

subtractively patterning the stack of material.

5. The method of claim 4 , wherein the stack of material comprises:

a chalcogenide material positioned below the sacrificial material.

6. The method of claim 4 , wherein the stack of material comprises:

an electrode material positioned below the sacrificial material.

7. The method of claim 4 , further comprising:

depositing a dielectric material between a plurality of separated lines that extend in the second direction, wherein the depositing is based at least in part on the patterning of the stack of material.

8. The method of claim 7 , further comprising:

removing the sacrificial line;

depositing a conductive material; and

forming a surface having conductive lines and dielectric areas.

9. The method of claim 4 , wherein subtractively patterning the stack of material comprises:

etching a middle electrode line of the first line stack to form a middle electrode that is electrically isolated in both the first direction and the second direction.

10. The method of claim 1 , wherein forming the first line stack or the second line stack comprises:

subtractively patterning using a pitch-multiplication process.

11. The method of claim 1 , wherein the sacrificial line comprises at least one of carbon, polyimide, silicon oxide, aluminum nitride, or silicon.

12. A method, comprising:

forming a first line stack oriented in a first direction, the first line stack including a first chalcogenide line over a first conductive line; and

forming a second line stack oriented in a second direction different from the first direction, the second line stack positioned above the first line stack and including a sacrificial line, wherein forming the first line stack comprises:

forming a stack of material including a chalcogenide material and a conductive material; and

subtractively patterning the stack of material using etching.

13. A method, comprising:

forming a first line stack oriented in a first direction, wherein the first line stack includes a sacrificial line over a first conductive line;

forming a chalcogenide line extending in the first direction by removing the sacrificial line and replacing material of the sacrificial line;

forming a second line stack overlaying the first line stack and oriented in a second direction different than the first direction; and

replacing a sacrificial material with a stack of materials that includes a first chalcogenide material and a conductive material.

14. The method of claim 13 , wherein forming the second line stack comprises:

forming a stack of material that includes a plurality of layers; and

subtractively patterning the stack of material using etching.

15. The method of claim 14 , wherein at least one layer of the plurality of layers includes a second chalcogenide material, a first conductive material, or a second conductive material.

16. The method of claim 13 , wherein forming the first line stack comprises:

forming a stack of material that includes the conductive material and the sacrificial material;

etching the stack of material to form the first line stack, wherein the first line stack includes a plurality of lines each isolated from one another by a gap;

filling each gap with a dielectric material; and

planarizing the stack of material to form a surface that includes chalcogenide lines and dielectric areas.

17. The method of claim 13 , wherein the first conductive line comprises at least one of tungsten, aluminum, copper, doped silicon, titanium nitride, or tantalum nitride.

18. A method, comprising:

forming a first line stack oriented in a first direction and including a first chalcogenide line over a first conductive line;

forming a sacrificial line oriented in a second direction different from the first direction and positioned above the first line stack, wherein a second chalcogenide line is positioned below the sacrificial line; and

forming a second conductive line oriented in the second direction by replacing the sacrificial line.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (2)
Continuation 14228104 · Mar 27, 2014
Related Publication 20160260776A1 · Sep 8, 2016