Apparatuses and methods for performing logical operations using sensing circuitry
View Patent ↗The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.
1. A system, comprising:
a host; and
a memory device coupled to the host and comprising an array coupled to sensing circuitry;
wherein the sensing circuitry comprises:
a first latch coupled to a sense line of the array; and
a second latch coupled to the first latch; and
wherein the sensing circuitry is controlled to accumulate, in the second latch, a result of:
a first operation phase of a logical operation; and
a number of intermediate operation phases of the logical operation;
wherein the first operation phase comprises sensing a memory cell coupled to the sense line;
wherein the number of intermediate operation phases comprise sensing a respective number of different memory cells coupled to the sense line, and wherein subsequent to the number of intermediate operation phases, an accumulated result of the logical operation is stored in the second latch.
2. The system of claim 1 , wherein the first latch is a latch of a sense amplifier and the second latch is a latch of a compute component.
3. The system of claim 1 , wherein the logical operation is at least one of:
an AND operation;
an OR operation;
a NAND operation; and
a NOR operation.
4. The system of claim 1 , wherein the memory cell and the respective number of different memory cells are each coupled to different access lines of the array.
5. The system of claim 1 , wherein the system is a server system.
6. The system of claim 1 , wherein the host is a processor external to the memory device.
7. The system of claim 6 , wherein the memory device includes a controller configured to execute instructions from the host.
8. The system of claim 1 , wherein the sensing circuitry is controlled to perform logical operations in addition to logical operations performed by the host in association with executing a set of instructions.
9. The system of claim 1 , wherein the array comprises DRAM (dynamic random access memory) cells, and wherein the sense line is one of a pair of complementary sense lines corresponding to a column of the array.
10. A system, comprising:
a host; and
a memory device coupled to the host and comprising a controller configured to control sensing circuitry coupled to an array to:
determine a data value serving as a first input of a logical operation via a sense amplifier coupled to a sense line of the array;
provide the determined data value to a latch of a compute component coupled to the sense amplifier; and
sense, via the sense amplifier, a number of data values stored in a number of memory cells coupled to the sense line, the number of data values serving as a respective number of additional inputs of the logical operation; and
wherein a determined result of the logical operation is stored in the latch of the compute component.
11. The system of claim 10 , wherein the compute component comprises transistors formed on pitch with memory cells of the array.
12. The system of claim 10 , wherein the sensing circuitry is controlled to store the result of the logical operation in the array without performing a sense line address access.
13. The system of claim 10 , wherein the compute component comprises:
a first and a second pair of cross coupled transistors;
a pair of pass transistors; and
a pair of invert transistors.
14. The system of claim 13 , wherein the compute component is configured to perform an accumulate function on the number of data values by enabling only one transistor of the pair of pass transistors.
15. A system, comprising:
a host; and
a memory device coupled to the host and comprising an array coupled to sensing circuitry, the sensing circuitry comprising:
a first latch coupled to a sense line of the array; and
a compute component comprising a second latch;
wherein the sensing circuitry is controlled to perform a logical operation by:
performing a first operation phase that includes:
activating a first access line of the array;
transferring, to the first latch from a memory cell coupled to the first access line and to the sense line, a data value corresponding to a first input of the logical operation; and
transferring, to the second latch, the data value corresponding to the first input;
performing a second operation phase that includes:
activating a second access line of the array;
transferring, to the first latch from a memory cell coupled to the second access line and to the sense line, a data value corresponding to a second input of the logical operation; and
transferring a result of the logical operation from the second latch to at least one of:
the array; and
the first latch.
16. The system of claim 15 , wherein the second latch is configured to remain activated during the second operation phase.
17. The system of claim 15 , wherein performing the first operation phase further comprises:
enabling a pair of pass transistors coupled to the first latch and to the second latch;
activating the second latch while the pair of transistors remain enabled such that the data value corresponding to the first input is transferred to the second latch; and
deactivating the first access line and the sense amplifier and disabling the pair of pass transistors.
18. The system of claim 17 , wherein performing the second operation phase further comprises:
enabling, based on a particular logical operation being performed, only one of the pair of pass transistors, wherein the second latch remains activated during the second operation phase; and
deactivating the second access line and the first latch and disabling the one of the pair of pass transistors.
19. The system of claim 15 , wherein the second operation phase is one of a number of intermediate operation phases each associated with sensing a memory cell coupled to a different access line in order to determine a data value of a memory cell corresponding to another input of the logical operation.
20. The system of claim 15 , wherein the host is a processor external to the memory device, and wherein the controller is configured to control the sensing circuitry to perform the logical operation without transferring data via an I/O line between the processor and the sensing circuitry.