IP Library Granted Patent US 10,026,457
Granted Patent B2
US 10,026,457 · App. 15/490,690 · Granted Jul 17, 2018

Device having multiple channels with calibration circuit shared by multiple channels

Inventors: Tetsuya Arai (Tokyo, JP); Junki Taniguchi (Tokyo, JP)
Assignee: Micron Technology, Inc.
G11C7/04H03K19/018507H03K19/018585
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Quick Facts
Patent No.
US 10,026,457
App. No.
15/490,690
Granted
Jul 17, 2018
Kind
B2
Abstract

An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second channel includes a second command control circuit independent of the first command control circuit. The calibration circuit is shared by the first channel and the second channel to generate a calibration code responsive to a calibration command generated responsive to a first calibration command from the first command control circuit and a second calibration command from the second command control circuit.

Claims (46)

1. A method for calibrating a semiconductor device, comprising:

receiving a first calibration command at a first set of terminals of the semiconductor device;

performing a first calibration operation for a first output circuit of the semiconductor device responsive to the first calibration command;

receiving a second calibration command at a second set of terminals of the semiconductor device;

performing a second calibration operation for a second output circuit of the semiconductor device responsive to the second calibration command;

receiving a first latch command at the first set of terminals, the first latch command is received after the first calibration operation has been finished and before the second calibration command is received; and

applying a first calibration code produced by the first calibration operation to the first output circuit responsive to the first latch command.

2. The method of claim 1 , wherein the second command is received after the first calibration operation has been finished.

3. The method of claim 1 , further comprising:

receiving a third calibration command at the first set of terminals; and

ignoring the third command when the third command has been received while the second calibration operation is being performed.

4. The method of claim 1 , further comprising:

receiving a second latch command at the second set of terminals, the second latch command is received after the second calibration operation has been finished; and

applying a second calibration code produced by the second calibration operation to the second output circuit responsive to the second latch command.

5. The method of claim 4 , wherein the applying the first calibration code produced by the first calibration operation to the first output circuit is executed without applying the first calibration code to the second output circuit.

6. The method of claim 4 , further comprising:

receiving a second latch command at the second set of terminals, the second latch command is received after the first calibration operation has been finished and before the second calibration command is received; and

applying the first calibration code to the second output circuit responsive to the second latch command.

7. The method of claim 1 , wherein the semiconductor device is coupled to a common resistor used in each of the first and second calibration operations.

8. A method for calibrating a semiconductor device, comprising:

receiving a first calibration command for a first output circuit of the semiconductor device;

performing a first calibration operation responsive to the first calibration command;

receiving a second calibration command for a second output circuit of the semiconductor device;

ignoring the second calibration command when the second calibration command has been received while the first calibration operation is being performed;

receiving a first latch command; and

applying a first calibration code produced by the first calibration operation to the first output circuit responsive to the first latch command.

9. The method of claim 8 , further comprising:

receiving a third calibration command for the second output circuit; and

performing a second calibration operation responsive to the third calibration command when the third command is received after the first calibration operation has been finished.

10. The method of claim 8 , wherein the applying the first calibration code produced by the first calibration operation to the first output circuit is executed without applying the first calibration code to the second output circuit.

11. The method of claim 8 , further comprising:

receiving a second latch command; and

applying the first calibration code to the second output circuit responsive to the second latch command.

12. The method of claim 9 , wherein the semiconductor device is coupled to a common resistor used in each of the first and second calibration operations.

13. A method for calibrating a semiconductor device, comprising:

receiving a first calibration command for a first output circuit of the semiconductor device;

performing a first calibration operation responsive to the first calibration command to produce a first calibration code;

receiving a first latch command to apply the first calibration code to the first output circuit; and

receiving a second latch command to apply the first calibration code to a second output circuit of the semiconductor device.

14. The method of claim 13 , further comprising:

receiving a second calibration command for the second output circuit; and

ignoring the second calibration command when the second calibration command has been received while the first calibration operation is being performed.

15. The method of claim 13 , further comprising:

receiving a second calibration command for the second output circuit; and

performing a second calibration operation responsive to the second calibration command to produce a second calibration code when the second calibration command is received after the first calibration operation has been finished.

16. The method of claim 15 , wherein the semiconductor device is coupled to a common resistor used in each of the first and second calibration operations.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050702/0451 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 4 TO PATENT SECURITY AGREEMENT Recorded May 4, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042405/0909 →
Priority Claims (1)
JP 2014-105195 · May 21, 2014 · national
Continuity (2)
Continuation 14695837 · Apr 24, 2015
Related Publication 20170221533A1 · Aug 3, 2017
Cited By (4)
US 12,231,106 US 12,249,969 US 12,579,058 US 12,695,453