Granted Patent B2

US 12,695,453 · App. 18/948,223 · Granted Jul 28, 2026

Inventor: Dean Gans (Nampa, ID)

H03K19/018585G06F13/4086G11C7/02G11C29/02G11C29/022G11C29/028G11C29/50008H03K19/0005G11C7/04G11C2029/4402G11C2207/2254

Abstract

Claims (15)

1 . An apparatus comprising:

a memory controller configured to enable ZQ stop to halt a ZQ calibration operation by providing a mode register write command to a memory of a plurality of memories coupled to an external resistance, the mode register write command configured to set a bit in a mode register of the memory.

2 . The apparatus of claim 1 , wherein the mode register write command is configured to enable ZQ stop by setting a value of the bit to 1.

3 . The apparatus of claim 1 , wherein the memory controller is configured to provide a second mode register write command to set the bit in the mode register to resume normal operation of ZQ calibration.

4 . The apparatus of claim 3 , wherein the second mode register write command is configured to set a value of the bit to 0.

5 . The apparatus of claim 1 , wherein the bit comprises operand 1 (OP[1]) of the mode register.

6 . The apparatus of claim 1 , wherein the memory controller is configured to provide a ZQ calibration command.

7 . A method comprising:

providing, from a memory controller to a memory device, a mode register write command to set at least one bit in a mode register to enable ZQ stop to halt a ZQ calibration operation for one or more programmable termination resistances; and

causing the ZQ calibration operation to be halted when ZQ stop is enabled, wherein the ZQ calibration operation is performed by a memory device of a set of memory devices coupled to an external resistor.

8 . The method of claim 7 , wherein the mode register write command sets the at least one bit to 1 to enable ZQ stop.

9 . The method of claim 7 , further comprising:

providing, from the memory controller to the memory device, a second mode register write command to set the at least one bit to disable ZQ stop.

10 . The method of claim 9 , wherein the second mode register write command sets the at least one bit to 0 to indicate normal operation of ZQ calibration.

11 . The method of claim 7 , wherein the at least one bit comprises operand 1 (OP[1]) of the mode register.

Continuity (6)

References Cited (264)