Granted Patent B2

US 12,231,106 · App. 18/607,063 · Granted Feb 18, 2025

Inventor: Dean Gans (Nampa, ID)

H03H11/28G11C7/10G11C29/025G11C29/028H03K19/0005H03H11/54

Abstract

Claims (50)

1. An apparatus comprising:

a memory controller configured to cause a memory to apply new calibration results to programmable termination resistances by performing operations comprising:

provide a register read command to a register of a memory;

receive, responsive to the register read command, at least one bit from the register of the memory;

determine, based on a value of the at least one bit from the register of the memory, availability or unavailability of new calibration results of a calibration operation associated with the programmable termination resistances; and

provide a latch command to the memory when the value of the at least one bit in the register of the memory indicates the availability of the new calibration results, wherein the latch command is configured to cause the memory to apply the new calibration results to the programmable termination resistances.

2. The apparatus of claim 1 , wherein the value of the at least one bit from the register of a memory includes a “0” value to indicate the unavailability of the new calibration results.

3. The apparatus of claim 1 , wherein the value of the at least one bit from the register of the memory includes a “1” value to indicate the availability of the new calibration results.

4. The apparatus of claim 1 , wherein the memory controller is further configured to:

provide a calibration command to cause the memory to perform the calibration operation associated with the programmable termination resistances.

5. The apparatus of claim 1 , wherein the calibration operation is performed using a shared external resistance.

6. The apparatus of claim 1 further comprising the memory.

7. The apparatus of claim 1 , wherein the calibration operation comprises a background calibration operation performed by the memory.

8. The apparatus of claim 1 , wherein the programmable termination resistances comprise pull-up and pull-down drivers.

9. The apparatus of claim 1 , wherein the operations further comprise:

provide the register read command at least a second time when the value of the at least one bit in the register of the memory indicates the unavailability of the new calibration results.

10. A system comprising:

at least one memory controller configured to:

provide a register read command;

receive, responsive to the register read command, at least one bit from a register; and

provide a latch command when a value of the at least one bit from the register indicates availability of new calibration results of a calibration operation;

first and second memory devices comprising programmable termination resistances, the first and second memory devices each configured to:

receive the register read command;

provide the at least one bit from the register;

receive the latch command; and

apply the new calibration results to the programmable termination resistances responsive to the latch command;

a shared external resistor coupled to a power supply voltage and the first and second memory devices, wherein the shared external resistor is configured to be used to perform the calibration operation; and

a memory bus coupled to the at least one memory controller and the first and second memory devices, wherein the memory bus is configured to:

transmit the register read command from the at least one controller to the first and second memory devices;

transmit, via a data line of the memory bus, the at least one bit from the first and second memory devices to the at least one memory controller; and

transmit the latch command from the at least one memory controller to the first and second memory devices.

11. The system of claim 10 , wherein the value of the at least one bit from the register includes a “0” value to indicate unavailability of the new calibration results.

12. The system of claim 10 , wherein the value of the at least one bit from the register of the memory includes a “1” value to indicate the availability of the new calibration results.

13. The system of claim 10 , wherein the at least one controller is further configured to:

provide a calibration command to cause at least one of the first or second memory device to perform the calibration operation.

14. The system of claim 10 , wherein the first memory device, the second memory device, or both the first and second memory device includes an arbitration engine configured to arbitrate for control of the shared external resistor.

15. A method comprising:

providing, by a memory controller, a register read command to a register of a memory;

receiving, by the memory controller and responsive to the register read command, a value of at least one bit in the register of the memory;

determining, based on the value of the at least one bit in the register of the memory, availability or unavailability of new calibration results of a calibration operation associated with programmable termination resistances of the memory; and

providing, by the memory controller, a latch command to the memory when the value of the at least one bit in the register of the memory indicates the availability of the new calibration results, wherein the latch command is configured to cause the memory to apply the new calibration results to the programmable termination resistances.

16. The method of claim 15 , wherein the value of the at least one bit in the register of a memory includes a “0” value to indicate the unavailability of the new calibration results.

17. The method of claim 15 , wherein the value of the at least one bit in the register of the memory includes a “1” value to indicate the availability of the new calibration results.

18. The method of claim 15 further comprising:

providing, by the memory controller, a calibration command to cause the memory to perform the calibration operation associated with the programmable termination resistances.

19. The method of claim 18 , wherein the calibration operation is performed using a shared external resistance.

20. The method of claim 15 , wherein the calibration operation comprises a background calibration operation performed by the memory.

21. A method comprising:

reading, by a memory controller, a bit from a mode register of a memory, wherein the bit represents a calibration flag, and wherein the bit has a first value or a second value different from the first value; and

sending, by the memory controller, a latch command to the memory when the bit representing the calibration flag has the first value, wherein the latch command causes the memory to apply results of a calibration operation.

Continuity (7)

References Cited (257)

Cited By (1)

US 12,695,453