Wear leveling for a memory device
Memory devices and methods to facilitate wear leveling operations in a memory device. In one such method, particular blocks of memory cells are excluded from experiencing wear leveling operations performed on the memory device. In at least one method, a user selects blocks of memory to be excluded from wear leveling operations performed on the remainder of blocks of the memory device. Selected blocks of memory are excluded from wear leveling operations responsive to a command initiated by a user identifying, either directly or indirectly, the selected blocks to be excluded.
1. A method of operating a memory device having an array of memory cells arranged in a plurality of blocks, the method comprising:
receiving a write command comprising information identifying a particular group of one or more blocks of the plurality of blocks to be excluded from wear leveling operations and having associated data to be stored to the particular group of one or more blocks;
storing the information identifying the particular group of one or more blocks to a non-volatile memory of the memory device as a portion of information identifying blocks to be excluded from wear leveling operations; and
performing one or more wear leveling operations only on a subset of the plurality of blocks responsive to the information identifying blocks to be excluded from wear leveling operations;
wherein the particular group of one or more blocks is not contained in the subset of the plurality of blocks.
2. The method of claim 1 , wherein receiving the write command further comprises receiving the write command from a host device coupled to the memory device and configured to communicate with the memory device.
3. The method of claim 1 , wherein performing the one or more wear leveling operations responsive to the information identifying blocks to be excluded from wear leveling operations further comprises performing the one or more wear leveling operations only on blocks of the plurality of blocks other than blocks comprising the particular group of one or more blocks.
4. The method of claim 1 , wherein identifying a particular group of one or more blocks comprises identifying a range of blocks of the plurality of blocks comprising the particular group of one or more blocks.
5. The method of claim 1 , wherein identifying a particular group of one or more blocks comprises identifying a start address and an ending address of blocks of the plurality of blocks comprising the particular group of one or more blocks.
6. The method of claim 1 , wherein identifying a particular group of one or more blocks comprises identifying a start address and a particular number indicative of a range of addresses following the start address.
7. The method of claim 1 , wherein the write command comprises a logical address and a flag having a value indicative that the logical address corresponds to a physical block address of a block of the plurality of blocks comprising the particular group of one or more blocks.
8. The method of claim 1 , wherein the write command comprises a logical address and a flag having a value indicative that the logical address is to be associated with a particular block of the plurality of blocks to be excluded from wear leveling operations.
9. A method of operating a memory device having an array of memory cells arranged in a plurality of blocks, the method comprising:
receiving a write command comprising information identifying a particular group of one or more blocks of the plurality of blocks to be excluded from wear leveling operations and having associated data to be stored to the particular group of one or more blocks;
storing the information identifying the particular group of one or more blocks to a non-volatile memory of the memory device as a portion of information identifying blocks to be excluded from wear leveling operations; and
performing one or more wear leveling operations on each block of the plurality of blocks other than the particular group of one or more blocks responsive to the information identifying blocks to be excluded from wear leveling operations.
10. The method of claim 9 , wherein performing one or more wear leveling operations further comprises performing one or more static wear leveling operations.
11. The method of claim 9 , wherein receiving the write command further comprises receiving a command generated external to the memory device.
12. The method of claim 11 , wherein identifying a particular group of one or more blocks of the plurality of blocks comprises identifying the blocks of the plurality of blocks comprising the particular group of one or more blocks.
13. The method of claim 9 , wherein the particular group of one or more blocks comprises a particular range of blocks of the plurality of blocks.
14. The method of claim 9 , wherein the plurality group of one or more blocks comprises a single memory partition.
15. The method of claim 9 , wherein each block of the plurality of blocks comprises an independently erasable block of memory cells.
16. The method of claim 9 , further comprising receiving the associated data to be stored in the one or more blocks of the particular group of one or more blocks, and storing the received data in the one or more blocks of the particular group of one or more blocks.
17. The method of claim 9 , wherein receiving the write command further comprises receiving the write command generated by a host coupled to the memory device.
18. The method of claim 17 , wherein the write command comprises a logical address and a flag having a flag value, where the flag value is indicative of whether the associated data should be stored in blocks of the plurality of blocks that are excluded from wear leveling operations.
19. The method of claim 17 , further comprising performing a write operation on one or more blocks of the particular group of one or more blocks responsive to the write command.
20. The method of claim 17 , further comprising performing the one or more wear leveling operations independent of direction from the host.
21. The method of claim 9 , wherein performing a wear leveling operation further comprises performing a wear leveling operation by copying data from a first block of the plurality of blocks to a second block of the plurality of blocks.
22. The method of claim 21 , wherein the first block and the second block comprise blocks other than blocks of the particular group of one or more blocks.
23. The method of claim 21 , further comprising performing an erase operation on the first block after copying data from the first block to the second block.
24. A method of wear leveling an array of memory cells arranged in a plurality of blocks, the method comprising:
receiving a write command comprising information indicating one or more blocks of the plurality of blocks to exclude from wear leveling operations and having associated data to be stored to the one or more excluded blocks; and
storing the information indicating one or more blocks of the plurality of blocks to exclude from wear leveling operations to the array of memory cells as a portion of information identifying blocks to be excluded from wear leveling operations; and
performing one or more wear leveling operations only on blocks of the plurality of blocks other than the one or more excluded blocks responsive to the information identifying blocks to be excluded from wear leveling operations.
25. The method of claim 24 , wherein performing one or more wear leveling operations further comprises performing one or more static wear leveling operations.
26. The method of claim 24 , wherein receiving the write command further comprises receiving a command generated external to the memory device.
27. The method of claim 24 , wherein the plurality of blocks comprises a single memory partition.
28. The method of claim 24 , wherein each block of the plurality of blocks comprises an independently erasable block of memory cells.
29. The method of claim 24 , further comprising receiving the associated data, and storing the received data in the one or more blocks of the plurality of blocks to exclude from the wear leveling operations.
30. A memory device, comprising:
an array of memory cells arranged in a plurality of blocks;
an interface configured to receive a write command comprising information identifying a particular group of blocks of the plurality of blocks and having associated data to be stored to the particular group of blocks, the write command having a flag that indicates to the memory device if the data associated with the write command is to be excluded from wear leveling operations; and
control circuitry, wherein the control circuitry is configured store the information identifying the particular group of one or more blocks to a non-volatile memory of the memory device as a portion of information identifying blocks to be excluded from wear leveling operations if the flag indicates that the data associated with the write command is to be excluded from wear leveling operations, and wherein the control circuitry is further configured to perform one or more wear leveling operations only on a subset of the plurality of blocks other than blocks of the particular group of blocks responsive to the information identifying blocks to be excluded from wear leveling operations.
31. The memory device of claim 30 , wherein the control circuitry is further configured to perform the one or more wear leveling operations independent of one or more commands received at the interface.
32. The memory device of claim 30 , wherein the array of memory cells comprises a single partition of memory cells.
33. The memory device of claim 30 , wherein the control circuitry is further configured to independently erase each block of the plurality of blocks.
34. The memory device of claim 30 , wherein the array of memory cells comprises a NAND configured array of flash memory cells.
35. The memory device of claim 30 , wherein the array of memory cells comprises a NOR configured array of flash memory cells.
36. The memory device of claim 30 , wherein the array of memory cells are configured as MLC and/or SLC memory cells.
37. The memory device of claim 30 , wherein the memory cells of the array comprise one of phase-change memory cells, nitride read-only memory cells, or ferroelectric field-effect transistor memory cells.
38. The memory device of claim 30 , wherein a wear leveling operation comprises an operation to copy data stored in a first block of the plurality of blocks to a second block of the plurality of blocks without changing a value of the copied data, where the first block and the second block each comprise blocks of the plurality of blocks other than blocks of the particular group of blocks.