Synchronous semiconductor memory device having on-die termination circuit and on-die termination method
A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.
1. A synchronous semiconductor memory device comprising:
a data output circuit adapted to generate data output up and down signals and to perform a data output operation synchronously to an external clock in response to the data output up and down signals; and
an on-die termination (ODT) circuit adapted to generate ODT up and down signals for performing an ODT operation synchronously to said external clock in response to the ODT up and down signals.
2. The device as claimed in 1 , wherein the data output circuit comprises:
a data output multiplexer adapted to multiplexing read data applied from at least one memory cell using at least one clock signal, to generate the data output up and down signals; and
an output driver adapted to perform the data output operation synchronized to the external clock, the output driver comprising,
a pull-up driver, and
a pull-down driver,
wherein the output driver controls an on operation and an off operation of the pull-up driver and the pull-down driver in response to a state of the data output up and down signals.
3. The device as claimed in 1 , wherein the ODT circuit comprises an ODT synchronous buffer adapted to receive an ODT command applied in response to a buffered clock signal generated by buffering the external clock, and outputting a synchronous ODT command in response to a first clock signal delay-locked to the external clock.
4. The device as claimed in 3 , wherein the ODT circuit further comprises:
an ODT gate adapted to pass through and latch the synchronous ODT command in response to the first clock signal and a second clock signal that has a fixed phase difference with respect to the first clock signal, to generate the ODT up and down signals.
5. The device as claimed in 3 , further comprising a delay-locked loop adapted to generate the first clock signal delay-locked to the external clock.
6. The device as claimed in 3 , wherein the phase difference between the first and second clock signals is based on a half cycle of the external clock.
7. The device as claimed in 3 , wherein the ODT synchronous buffer comprises:
a delay adapted to delay the ODT command for a fixed time;
a first flip-flop adapted to latch an output of the delay in response to the buffered clock signal; and
a second flip-flop adapted to latch an output of the first flip-flop in response to the first clock signal, to generate the synchronous ODT command.
8. The device as claimed in 1 , wherein the ODT circuit comprises an ODT driver adapted to perform an ODT driving operation synchronized to the external clock, by controlling an ON operation and an OFF operation of a pull-up resistance and a pull-down resistance in response to a state of the ODT up and down signals.
9. The device as claimed in 8 , wherein the ODT driver comprises:
an output pad; and
a plurality of unit drivers, wherein each of said unit drivers comprises,
a pull-up resistance having a first end directly connected to a common node,
a pull-down resistance having a first end directly connected to the common node,
a pull-up transistor having a drain connected to a second end of the pull-up resistance, a source connected to a power voltage, and a gate adapted to respond to the ODT up signal, and
a pull-down transistor having a drain connected to second end of the pull-down resistance, a source connected to a ground voltage, and a gate adapted to respond to the ODT down signal,
wherein the common node of each of the unit drivers is connected to the output pad.
10. The device as claimed in 9 , wherein the plurality of unit drivers comprises:
at least two pull-up resistances with different values; and
at least two pull-down resistances with different values.
11. The device as claimed in 1 , wherein the ODT circuit comprises an ODT controller adapted to output an up enable signal and a down enable signal in response to an external or internal control signal.
12. The device as claimed in 11 , wherein said ODT controller includes at least one fuse for generating an internal control signal.
13. The device as claimed in 11 , wherein when said ODT controller outputs the up and down enable signals in response to an external control signal, a mode register set code is externally received.