On-die system and method for controlling termination impedance of memory device data bus terminals
A system for controlling the termination impedance of memory device data bus terminals is fabricated on the same die as the memory device. The system includes a termination resistor connected to each data bus terminal, which is connected in parallel with several transistors that are selectively turned on to adjust the termination impedance. The transistors are controlled by a circuit that determines the resistance of the termination resistor and turns on the correct number of transistor to properly set the termination impedance. In one example, the resistance of the termination resistor is determined by directly measuring a resistor of the same type as the termination resistor. In another example, the resistance of the termination resistor is determined indirectly by measuring parameters that affect the resistance of the termination resistor. In either case, the system can maintain the termination impedance of the data bus terminals constant despite changes in the termination resistor.
1. A termination system comprising:
a termination resistor formed in a semiconductor die;
a transistor coupled between the termination resistor and an externally accessible terminal;
a first sensor configured to sense a temperature of the semiconductor die;
a second sensor configured to sense a value of a supply supplied to the transistor;
a third sensor configured to sense a resistance of the transistor;
control logic coupled to the first, second, and third sensors and configured to generate a control signal indicative of an impedance at the externally accessible terminal, wherein the control signal is based at least in part on the temperature of the semiconductor die, the value of the supply, and the resistance of the transistor; and
trim code register coupled to the control logic and configured to convert the control signal to digital activation signals used to change the impedance at the externally accessible terminal.
2. The termination system of claim 1 , wherein the transistor is coupled to the control signal.
3. The termination system of claim 1 wherein the resistor comprises a polysilicon resistor.
4. A termination system comprising:
an externally accessible terminal;
first and second transistors;
a first termination resistor formed on a semiconductor die, the first resistor coupled between a first supply and the first transistor, and the first transistor coupled between the first termination resistor and the externally accessible terminal;
a second termination resistor formed on the semiconductor die, the second resistor coupled between a second supply and the second transistor, the second transistor coupled between the second termination resistor and the externally accessible terminal;
a first sensor configured to sense a temperature of the semiconductor die;
a second sensor configured to sense a value of the first supply;
a third sensor configured to sense a resistance of the first and second transistors;
control logic coupled to the first and second sensors and configured to generate a control signal indicative of an impedance at the externally accessible terminal, wherein the control signal is based at least in part on the temperature of the semiconductor die, the value of the supply, and the resistance of the first and second transistors; and
trim code register coupled to the control logic and configured to convert the control signal to digital activation signals used to change the impedance at the externally accessible terminal.
5. The termination system of claim 4 wherein the first and second resistors comprise polysilicon resistors.
6. The termination system of claim 4 wherein the first transistor comprises an NMOS transistor and the second transistor is a PMOS transistor.
7. The termination system of claim 6 wherein a gate of the first transistor is coupled to the control signal and a gate of the second transistor is coupled through an inverter to the control signal.
8. The termination system of claim 6 wherein the first supply is greater than the second supply.
9. A method of terminating a terminal using a resistor and a transistor, the method comprising:
sensing at least two conditions which affect a resistance of the resistor, the at least two conditions other than being the resistance of the resistor;
sensing a resistance of the transistor;
determining the resistance of the resistor based in part on the at least two conditions;
generating a control signal indicative of an impedance at the terminal based at least in part on a sum of the resistance of the resistor and the resistance of the transistor; and
coupling the resistor to the terminal through the transistor based in part upon the control signal.
10. The method of claim 9 , wherein sensing the at least two conditions comprises sensing at least a temperature of a semiconductor die having the resistor thereon.
11. The method of claim 10 , wherein sensing the at least two conditions comprises sensing at least a value of a supply voltage supplied to the transistor.
12. The method of claim 9 , wherein the resistance of the transistor comprises an on resistance of the transistor.
13. The method of claim 12 , wherein determining the resistance of the resistor comprises determining the resistance based at least in part on the temperature of the semiconductor die and the value of the supply, and generating the control signal comprises adding the resistance of the transistor to the resistance of the resistor
14. A method of terminating a terminal comprising:
sensing a temperature of a semiconductor die, the semiconductor die having a resistor formed thereon;
sensing a value of a voltage supply supplied to a transistor;
sensing a resistance of a transistor;
generating a control signal indicative of an impedance at the terminal based at least in part upon the temperature of the semiconductor die, the value of the voltage supply, and the resistance of the transistor;
converting the control signal into digital activation signals used to change the impedance at the terminal; and
coupling the resistor to the terminal through the transistor based in part upon the control signal.
15. The method of claim 14 , wherein generating the control signal comprises determining an impedance of the resistor based in part on the temperature of the semiconductor die and the value of the voltage supply.
16. The method of claim 14 , wherein generating the control signal comprises determining an impedance of the resistor based in part on the temperature of the semiconductor die and the value of the voltage supply, and adding the resistance of the transistor to the impedance of the resistor.
17. The method of claim 14 , wherein the resistance of the transistor comprises an on resistance of the transistor.