Semiconductor device capable of controlling OCD and ODT circuits and control method used by the semiconductor device
Provided is a semiconductor device capable of controlling an on-die-termination (ODT) circuit and an off-chip-driver (OCD) circuit and a control method used by the semiconductor device. The semiconductor device includes a control code generation unit generating a control code in response to a control signal, an addition unit adding an adjustment code to the control code to produce an adjusted control code, and an ODT circuit, wherein an impedance of the ODT circuit is adjusted in response to the adjusted control code. The semiconductor device can adjust the control code more precisely by adding or subtracting the adjustment code to or from the control code. Accordingly, the impedance of an OCD circuit or ODT circuit can be adjusted more precisely.
1. A semiconductor device comprising:
a control code generation unit generating a control code in response to a control signal;
an addition unit adding a first adjustment code to the control code to generate an adjusted control code; and
an on-die-termination (ODT) circuit, wherein an impedance of the ODT circuit is adjusted in response to the adjusted control code,
wherein the control signal and the first adjustment code are generated in response to an external mode register set signal.
2. The device of claim 1 , wherein the ODT circuit comprises a plurality of transistors,
wherein the transistors are turned on or off in response to the adjusted control code to adjust the impedance of the ODT circuit.
3. The device of claim 1 , wherein a total bit count of the control code is greater than a total bit count of the first adjustment code, and a starting bit position of the control code to which the first adjustment code is added may vary.
4. The device of claim 1 , further comprising an off-chip-driver (OCD) circuit having an impedance adjusted in response to the adjusted control code.
5. The device of claim 4 , wherein the OCD circuit comprises a plurality of transistors,
wherein the transistors are turned on or off in response to the adjusted control code to adjust the impedance of the OCD circuit.
6. The device of claim 1 , wherein the control signal is generated in response to an external reference resistance, and the control code generation unit is a calibration loop removing noise from the control signal and generating the control code.
7. A control method comprising:
generating a control code in response to a control signal;
adding a first adjustment code to the control code to generate an adjusted control code; and
adjusting an impedance of an ODT circuit in response to the adjusted control code,
wherein the control signal and the first adjustment code are generated in response to an external mode register set signal.
8. The method of claim 7 , wherein, a plurality of transistors included in the ODT circuit are turned on or off to adjust the impedance of the ODT circuit.
9. The method of claim 7 , wherein a total bit count of the control code is greater than a total bit count of the first adjustment code, and a starting bit position of the control code to which the first adjustment code is added may vary.
10. The method of claim 7 , further comprising adjusting the impedance of an OCD circuit in response to the adjusted control code.
11. The method of claim 10 , wherein, a plurality of transistors included in the OCD circuit are turned on or off to adjust the impedance of the OCD circuit.
12. The method of claim 7 , wherein the control signal is generated in response to an external reference resistance, and noise is removed from the control signal and the control code is generated.
13. A semiconductor device comprising:
a control code generation unit generating a control code in response to a control signal;
an addition unit generating a second adjustment code from a first adjustment code and adding the second adjustment code to the control code to generate an adjusted control code; and
an on-die-termination (ODT) circuit, an impedance of the ODT circuit being adjusted in response to the adjusted control code,
wherein the second adjustment code comprises a lower, middle, and upper bit group,
wherein each bit of the lower bit group is 0, the middle bit group corresponds to the first adjustment code, and each of the bits of the upper bit group are set to the most significant bit of the first adjustment code.
14. A control method comprising:
generating a control code in response to a control signal;
selecting a starting bit position SBP of the control code having a total bit count CTBC;
copying the bits of the first adjustment code having a total bit count of ATBC to a second adjustment code starting at bit position SBP where the second adjustment code has a total bit count equal to CTBC;
setting the bits of the second adjustment code below bit position SBP-ATBC+1 to 0;
setting the bits of the second adjustment code above bit position SBC to the most significant bit of the first adjustment code;
adding the second adjustment code to the control code to produce an adjusted control code; and
adjusting an impedance of an ODT circuit in response to the adjusted control code,
wherein SBP, ATBC, and CTBC are integers greater than 0.