IP Library › Granted Patent US 7,646,213
Granted Patent B2
US 7,646,213 · App. 11/804,176 · Granted Jan 12, 2010

On-die system and method for controlling termination impedance of memory device data bus terminals

Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 7,646,213
App. No.
11/804,176
Granted
Jan 12, 2010
Kind
B2
Abstract

A system for controlling the termination impedance of memory device data bus terminals is fabricated on the same die as the memory device. The system includes a termination resistor connected to each data bus terminal, which is connected in parallel with several transistors that are selectively turned on to adjust the termination impedance. The transistors are controlled by a circuit that determines the resistance of the termination resistor and turns on the correct number of transistor to properly set the termination impedance. In one example, the resistance of the termination resistor is determined by directly measuring a resistor of the same type as the termination resistor. In another example, the resistance of the termination resistor is determined indirectly by measuring parameters that affect the resistance of the termination resistor. In either case, the system can maintain the termination impedance of the data bus terminals constant despite changes in the termination resistor.

Claims (34)

1. A termination circuit fabricated on a semiconductor die along with an electronic device having an externally accessible terminal, the termination circuit comprising:

a programmable on-die termination (“ODT”) circuit coupled to the externally accessible terminal, the programmable ODT circuit providing the externally accessible terminal with an impedance using the combination of a terminating resistor and a controllable impedance element having an impedance that is controlled by at least one programming signal received by the programmable ODT circuit; and

a programming circuit operable to determine the approximate impedance of the terminating resistor and to provide the at least one programming signal to the ODT circuit so that the impedance provided by the combination of the terminating resistor and the controllable impedance element is substantially equal to a predetermined target impedance, the programming circuit comprising:

a test resistor having impedance characteristics that substantially match the impedance characteristics of the terminating resistor; and

a measurement circuit for measuring the impedance of the test resistor, the measurement circuit comprising:

a precision resistor having a fixed impedance coupled in series with the test resistor between first and second predetermined voltages to form a voltage divider having an output node between the precision resistor and the test resistor;

an analog-to-digital converter having an input coupled to the output node, the analog-to-digital converter generating a binary output signal indicative of the impedance of the test resistor; and

a register generating a plurality of the programming signals based on the binary output signal.

2. The termination circuit of claim 1 wherein the terminating resistor comprises a polysilicon resistor.

3. The termination circuit of claim 1 wherein the measurement circuit further comprises a transistor switch coupled in series with the precision resistor and the test resistor between the first and second predetermined voltage for selectively enabling the voltage divider.

4. The termination circuit of claim 1 wherein the test resistor comprises an Naa resistor.

5. The termination circuit of claim 1 wherein the programming circuit comprises:

a plurality of sensors providing sensor output signals indicative of conditions that affect the impedance of the terminating resistor;

a control logic circuit coupled to receive the sensor output signals from the plurality of sensors, the control logic circuit providing an output signal based on the sensor output signals indicative of the impedance of the terminating resistor; and

a register storing digital signals corresponding to the output signal from the control logic circuit, the register generating a plurality of the programming signals corresponding to the stored digital signals.

6. The termination circuit of claim 5 wherein the plurality of sensors comprise a temperature sensor providing an output signal corresponding to the temperature of the semiconductor die.

7. The termination circuit of claim 5 wherein the plurality of sensors comprise a voltage sensor providing an output signal corresponding to a supply voltage applied to the semiconductor die.

8. The termination circuit of claim 5 wherein the programmable ODT circuit comprises an enable transistor coupled in series with the externally accessible terminal and the terminating resistor, and wherein the plurality of sensors comprise a sensor measuring the impedance of the enable transistor in its conductive condition and providing an output signal corresponding thereto.

9. The termination circuit of claim 1 wherein the programmable ODT circuit comprises a plurality of MOSFET transistors connected with their respective sources and drains in parallel with the terminating resistor and their respective gates coupled to receive a respective control signals derived from the at least one programming signal provided by the programming circuit.

10. A method of terminating an externally accessible terminal of an integrated circuit using the combination of a terminating resistor and a controllable impedance element fabricated as part of the integrated circuit, the method comprising:

determining the approximate impedance of the terminating resistor by measuring the impedance of a test resistor fabricated on a semiconductor die of the integrated circuit, the test resistor having impedance characteristics that substantially match the impedance characteristics of the terminating resistor, the impedance of a test resistor being measured by:

coupling a precision resistor in series with the test resistor between first and second predetermined voltage to form a voltage divider having an output node between the precision resistor and the test resistor;

determining the amplitude of the voltage at the output node of the voltage divider; and

using the determined voltage amplitude to determine the impedance of the test resistor; and

adjusting the impedance of the controllable impedance element as a function of the determined impedance so that the impedance provided by the combination of the terminating resistor and the controllable impedance element is substantially equal to a predetermined target impedance.

11. The method of claim 10 , further comprising digitizing the voltage at the output node of the voltage divider before using the determined voltage amplitude to determine the impedance of the test resistor.

12. The method of claim 10 wherein the test resistor comprises an Naa resistor.

13. The method of claim 10 wherein the act of determining the approximate impedance of the terminating resistor comprises

sensing a plurality of conditions that affect the impedance of the terminating resistor; and

using the sensed conditions to determine the impedance of the terminating resistor.

14. The method of claim 13 wherein the act of sensing a plurality of conditions that affect the impedance of the terminating resistor comprises sensing the temperature of a semiconductor die in which the integrated circuit is fabricated.

15. The method of claim 13 wherein the act of sensing a plurality of conditions that affect the impedance of the terminating resistor comprises sensing the magnitude of a supply voltage applied to the integrated circuit.

16. The method of claim 10 wherein the integrated circuit comprises an integrated circuit memory device.

17. The method of claim 16 wherein the integrated circuit memory device comprises an integrated circuit dynamic random access memory device.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2007
From: KAO, DAVID
To: MICRON TECHNOLOGY, INC.
Reel/Frame 019386/0080 →
Continuity (1)
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