Apparatuses and methods for calibrating adjustable impedances of a semiconductor device

1. A method comprising:

performing a ZQ calibration operation to determine calibration parameters for output driver impedance;

setting a value in a mode register when the calibration parameters comprise new calibration parameters;

receiving a latch command; and

applying the calibration parameters responsive to the latch command.

2. The method of claim 1 , further comprising: receiving a mode register read command; and

providing the value responsive to the mode register read command, wherein the latch command is received responsive to the value.

3. The method of claim 1 , wherein the ZQ calibration operation comprises a background calibration operation.

4. The method of claim 1 , further comprising:

arbitrating for control of an external resistance to perform the ZQ calibration operation.

5. The method of claim 1 , wherein the ZQ calibration operation is performed responsive to a command.

6. The method of claim 1 , wherein the ZQ calibration operation is performed responsive to power up of a semiconductor device.

7. The method of claim 1 , wherein the ZQ calibration operation is performed within a time interval.

8. The method of claim 7 , wherein the time interval is periodic.

9. The method of claim 1 , further comprising:

setting a value in the mode register to indicate that the ZQ calibration operation has been completed.

10. The method of claim 1 , wherein applying the calibration parameters comprises loading calibration values into pull-down and pull-up drivers.

11. An apparatus comprising:

a mode register;

programmable termination resistances having a programmable impedance; and

an impedance calibration circuit coupled to the calibration terminal and configured to perform a ZQ calibration operation to determine calibration parameters for the programmable termination resistances,

wherein the impedance calibration circuit is further configured to set a value in the mode register when the calibration parameters comprise new calibration parameters, and

wherein the impedance calibration circuit is further configured to apply the calibration parameters responsive to a latch command.

12. The apparatus of claim 11 , wherein the impedance calibration circuit is further configured to provide the value in response to a mode register read command.

13. The apparatus of claim 11 , wherein the ZQ calibration operation comprises a background calibration operation.

14. The apparatus of claim 11 , further comprising:

an arbitration engine configured to arbitrate for control of an external resistance to perform the ZQ calibration operation.

15. The apparatus of claim 11 , wherein the impedance calibration circuit is configured to perform the ZQ calibration operation responsive to a command.

16. The apparatus of claim 11 , wherein the impedance calibration circuit is configured to perform the ZQ calibration operation responsive to power up of a semiconductor device.

17. The apparatus of claim 11 , wherein the impedance calibration circuit is configured to perform the ZQ calibration operation within a time interval.

18. The apparatus of claim 17 , wherein the time interval is periodic.

19. The apparatus of claim 11 , wherein the impedance calibration circuit is further configured to set a value in the mode register to indicate that the ZQ calibration operation has been completed.

20. The apparatus of claim 11 , wherein applying the calibration parameters comprises loading calibration values into pull-down and pull-up drivers.