Apparatus having dice to perorm refresh operations
Some embodiments include an apparatus that comprise an interface chip having an oscillator to produce an original clock signal, a first memory chip having first memory cells, and a second memory chip having second memory cells. The first memory cells may be refreshed in response to a first clock signal based on the original clock signal. The second memory cells may be refreshed in response to a second clock signal based on the original clock signal.
1. An apparatus comprising:
an interface chip comprising an oscillator to produce an original clock signal;
a first memory chip comprising a first terminal to receive a first clock signal in response to the original clock signal, a second terminal to be supplied with a first control signal, and first memory cells subject to a first data refresh operation in response to the first clock signal when the first control signal is active; and
a second memory chip comprising a third terminal to receive a second clock signal in response to the original clock signal, a fourth terminal to be supplied with a second control signal, and second memory cells subject to a second data refresh operation in response to the second clock signal when the second control signal is active.
2. The apparatus of claim I wherein the second and fourth terminals are to independently receive the first and second control signals from the interface chip.
3. The apparatus of claim 1 , wherein the first and second terminals are electrically coupled in series to the oscillator of the interface chip.
4. The apparatus of claim 1 , wherein the first and second terminals are electrically coupled in parallel to the oscillator of the interface chip.
5. An apparatus comprising:
an interface chip comprising an oscillator to provide an oscillator signal;
a first memory chip on which a first refresh operation is performed in response to a first refresh enable signal to be supplied at a first node and a first oscillator enable signal to be supplied at a second node; and
a second memory chip on which a second refresh operation is performed in response to a second refresh enable signal to be supplied at a third node and a second oscillator enable signal to be supplied at a fourth node,
wherein the first and third nodes are to receive;, the interface chip, the first and second refresh enable signals independently of each other, and wherein the second and fourth nodes are to receive, based on the oscillator signal, the first and second oscillator enable signals in different timing values from each other.
6. The apparatus of claim 5 ,
wherein the first memory chip comprises a first delay circuit to delay the second oscillator enable signal to supply the first oscillator enable signal to the second node, and
wherein the second memory chip comprises a second delay circuit delay the oscillator signal to supply the second oscillator enable signal to the fourth node and the first delay circuit.
7. The apparatus of claim 6 , wherein first delay circuit and the second delay circuit have a same delay amount.
8. The apparatus of claim 5 ,
wherein the first memory chip comprises a first delay circuit to delay the oscillator signal to supply the first oscillator enable signal to the second node,
and wherein the second memory chip comprises a second delay circuit to delay the oscillator signal to supply the second oscillator enable signal to the fourth node.
9. The apparatus of claim 8 , wherein the first delay circuit and the second delay circuit have different delay amounts from each other.
10. The apparatus of claim 5 , wherein the interface chip comprises:
a first delay circuit to delay the second oscillator enable signal to supply the first oscillator enable signal to the second node, and
a second delay circuit to delay the oscillator signal to supply the second oscillator enable signal to the fourth node and the first delay circuit.
11. The apparatus of claim 10 , wherein the first delay circuit and the second delay circuit have a same delay amount.
12. The apparatus of claim 5 , wherein the interface chip comprises:
a first delay circuit to delay the oscillator signal to supply the first oscillator enable signal to the second node, and
a second delay circuit to delay the oscillator signal to supply the second oscillator enable signal to the fourth node.
13. The apparatus of claim 12 , wherein the first delay circuit and the second delay circuit have different delay amounts from each other.
14. The apparatus of claim 5 , wherein the oscillator activated in response to a reset signal supplied thereto.
15. The apparatus of claim 5 , wherein the first and second memory chips are stacked over each other.
16. The apparatus of claim 5 , wherein the first and second refresh operations are performed with different timing values from each other, when the first and third nodes receive the first and second refresh enable signals substantially simultaneously.