IP Library Granted Patent US 10,770,470
Granted Patent B2
US 10,770,470 · App. 15/457,473 · Granted Sep 8, 2020

Memory array having connections going through control gates

Inventors: Toru Tanzawa (Adachi, JP); Tamotsu Murakoshi (Kawasaki, JP); Deepak Thimmegowda (Boise, ID)
Assignee: Micron Technology, Inc.
H01L27/11556G11C16/0483H01L27/11521H01L27/11529H01L27/11548H01L27/11568H01L27/11573H01L27/11575H01L27/11582H01L29/66833H01L29/7926
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Quick Facts
Patent No.
US 10,770,470
App. No.
15/457,473
Granted
Sep 8, 2020
Kind
B2
Abstract

Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.

Claims (47)

1. An apparatus comprising:

a substrate;

a memory cell string including a body;

a first control gate located in a first level of the apparatus and along a first portion of the body;

a second control gate located in a second level of the apparatus and along a second portion of the body; and

a connection coupled to the second control gate and to a transistor, the transistor having at least a portion formed in the substrate, the connection including a first portion going through a first portion of the first control gate, and a second portion going through a second portion of the first control gate.

2. The apparatus of claim 1 , further comprising an opening through the first control gate, wherein the portion of the connection going through the portion of the first control gate is inside the opening.

3. The apparatus of claim 2 , wherein the first control gate includes an edge, the second control gate includes an edge, and the opening is between the edge of the first control gate and the edge of the second control gate.

4. The apparatus of claim 3 , wherein the distance between the body and the edge of the first control gate is greater than a distance between the body and the edge of the second control gate.

5. An apparatus comprising:

a substrate;

a memory cell string including a body;

a first control gate located in a first level of the apparatus and along a first portion of the body;

a second control gate located in a second level of the apparatus and along a second portion of the body;

a connection coupled to the second control gate and to a transistor, the transistor having at least a portion formed in the substrate, the connection including a portion going through a portion of the first control gate;

an opening through the first control gate, wherein the portion of the connection going through the portion of the first control gate is inside the opening;

a third control gate located in a third level of the apparatus and along a third portion of the body; and

an additional connection coupled to the third control gate and to an additional transistor, the additional transistor having at least a portion formed in the substrate, the additional connection including a portion going through an additional opening in the first control gate.

6. An apparatus comprising:

a substrate;

a memory cell string including a body;

a first control gate located in a first level of the apparatus and along a first portion of the body;

a second control gate located in a second level of the apparatus and along a second portion of the body; and

a connection coupled to the second control gate and to a transistor, the transistor having at least a portion formed in the substrate, the connection including a portion going through a portion of the first control gate, further comprising a third control gate located in a third level of the apparatus and along a third portion of the body, wherein the connection includes another portion going through a portion of the third control gate.

7. An apparatus comprising:

a first control gate and a second control gate in different levels of a device over a substrate of the device;

a first opening in a first area of the device between an edge of the first control gate and an edge of the second control gate;

a second opening in a second area of the device between the edge of the first control gate and the edge of the second control gate;

a connection coupling the second control gate to a conductive contact located between the substrate and the first control gate, wherein a first portion of the connection is inside the first opening, and a second portion of the connection is inside the second opening.

8. The apparatus of claim 7 , wherein a bottom of the opening is coupled to the conductive contact.

9. The apparatus of claim 7 , wherein the opening includes a portion going through the first control gate.

10. The apparatus of claim 9 , further comprising a dielectric material between the first control gate and the portion of the opening going through the first control gate.

11. An apparatus comprising:

a first control gate and a second control gate in different levels of a device over a substrate of the device;

an opening in an area of the device between an edge of the first control gate and an edge of the second control gate; and

a connection coupling the second control gate to a conductive contact located between the substrate and the first control gate, wherein a portion of the connection is inside the opening, wherein the connection includes:

a first segment coupled to the second control gate and extending in a direction perpendicular to the substrate;

a second segment in the opening; and

a third segment coupled to the first segment and the second segment.

12. An apparatus comprising:

a first group of control gates and a second group of control gates on different levels of a device over a substrate of the device;

an opening through the first group of control gates; and

a connection coupling a control gate in the second group of control gates to a conductive contact located between the first and second groups of control gates and the substrate, wherein the connection includes a portion inside the opening.

13. The apparatus of claim 12 , further comprising a dielectric material between the first group of control gates and the connection.

14. The apparatus of claim 12 , further comprising:

an additional opening through the first group of control gates;

an additional connection coupling an additional control gate in the second group of control gates to an additional conductive contact located between the first and second groups of control gates and the substrate, wherein the additional connection includes a portion inside the additional opening.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 21, 2023
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP, LLC
Reel/Frame 064988/0210 →
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050702/0451 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 4 TO PATENT SECURITY AGREEMENT Recorded May 4, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042405/0909 →
Continuity (2)
Division 13599793 · Aug 30, 2012
Related Publication 20170250190A1 · Aug 31, 2017
Cited By (3)
US 12,193,236 US 12,356,614 US 12,563,735