Input buffer circuit
Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes: a first amplifier that provides first and second intermediate voltages responsive to first and second input voltages; first and second voltage terminals; a circuit node; a first transistor coupled between the first voltage terminal and the circuit node and is turned on responsive to at least one of the first and second intermediate voltages; a second amplifier including first and second inverters, at least one of the first and second inverters being coupled between the circuit node and the second voltage terminal; and first and second output nodes, the first output node being coupled to an input node of the first inverter and an output node of the second inverter, and the second output node being coupled to an output node of the first inverter and an input node of the second inverter.
1. An apparatus comprising:
a first amplifier configured to provide first and second intermediate voltages responsive to first and second input voltages;
first and second voltage terminals;
a circuit node;
an additional circuit node, wherein the circuit node and the additional circuit node are isolated from each other;
a first transistor coupled between the first voltage terminal and the circuit node and configured to be turned on responsive to at least one of the first and second intermediate voltages;
a second transistor coupled between the first voltage terminal and the additional circuit node;
a second amplifier comprising first and second inverters, the first inverter coupled between the circuit node and the second voltage terminal, wherein the first transistor is configured to be turned on responsive to the first intermediate voltage and the second transistor is configured to be turned on responsive to the second intermediate voltage; and
first and second output nodes, the first output node being coupled to an input node of the first inverter and an output node of the second inverter, and the second output node being coupled to an output node of the first inverter and an input node of the second inverter.
2. The apparatus of claim 1 , wherein the second amplifier is configured to be activated responsive to either the first intermediate voltage exceeding a threshold voltage of the first transistor or the second intermediate voltage exceeding a threshold voltage of the second transistor.
3. The apparatus of claim 1 , further comprising a control circuit including a second transistor having a gate supplied with one of the first and second intermediate voltages and one of a source and a drain coupled to a gate of the first transistor.
4. The apparatus of claim 1 , further comprising a control circuit including:
a second transistor having a gate supplied with the first intermediate voltage and one of a source and a drain coupled to a gate of the first transistor; and
a third transistor having a gate supplied with the second intermediate voltage and one of a source and a drain coupled to the gate of the first transistor.
5. The apparatus of claim 4 , further comprising:
a fourth transistor having one of a source and a drain supplied with the first intermediate voltage and an other of the source and the drain coupled to the first output node; and
a fifth transistor having one of a source and a drain supplied with the second intermediate voltage and an other of the source and the drain coupled to the second output node.
6. The apparatus of claim 5 , wherein the fourth transistor has a gate coupled to the second output node and the fifth transistor has a gate coupled to the first output node.
7. The apparatus of claim 5 , wherein the fourth transistor has a gate coupled to the one of the source and the drain of the second transistor and the fifth transistor has a gate coupled to the one of the source and the drain of the third transistor.
8. The apparatus of claim 7 , wherein the fourth and fifth transistors are configured to be deactivated when a voltage of the first output node or the second output node exceeds a threshold voltage of the fourth transistor and the fifth transistor.
9. An apparatus comprising:
a first amplifier configured to provide first and second intermediate voltages responsive to first and second input voltages;
first and second voltage terminals;
a circuit node;
a first transistor coupled between the first voltage terminal and the circuit node and configured to be turned on responsive to at least one of the first and second intermediate voltages;
a second amplifier comprising first and second inverters, at least one of the first and second inverters being coupled between the circuit node and the second voltage terminal;
first and second output nodes, the first output node being coupled to an input node of the first inverter and an output node of the second inverter, and the second output node being coupled to an output node of the first inverter and an input node of the second inverter; and
a control circuit including a second transistor having a gate supplied with one of the first and second intermediate voltages and one of a source and a drain coupled to a gate of the first transistor.
10. An apparatus comprising:
a first amplifier configured to provide first and second intermediate voltages responsive to first and second input voltages;
first and second voltage terminals;
a circuit node;
a first transistor coupled between the first voltage terminal and the circuit node and configured to be turned on responsive to at least one of the first and second intermediate voltages;
a second amplifier comprising first and second inverters, at least one of the first and second inverters being coupled between the circuit node and the second voltage terminal;
first and second output nodes, the first output node being coupled to an input node of the first inverter and an output node of the second inverter, and the second output node being coupled to an output node of the first inverter and an input node of the second inverter; and
a control circuit including:
a second transistor having a gate supplied with the first intermediate voltage and one of a source and a drain coupled to a gate of the first transistor; and
a third transistor having a gate supplied with the second intermediate voltage and one of a source and a drain coupled to the gate of the first transistor.
11. The apparatus of claim 10 , further comprising:
a fourth transistor having one of a source and a drain supplied with the first intermediate voltage and an other of the source and the drain coupled to the first output node; and
a fifth transistor having one of a source and a drain supplied with the second intermediate voltage and an other of the source and the drain coupled to the second output node.
12. The apparatus of claim 11 , wherein the fourth transistor has a gate coupled to the second output node and the fifth transistor has a gate coupled to the first output node.
13. The apparatus of claim 11 , wherein the fourth transistor has a gate coupled to the one of the source and the drain of the second transistor and the fifth transistor has a gate coupled to the one of the source and the drain of the third transistor.
14. The apparatus of claim 13 , wherein the fourth and fifth transistors are configured to be deactivated when a voltage of the first output node or the second output node exceeds a threshold voltage of the fourth transistor and the fifth transistor.