Reducing programming disturbance in memory devices

1. A method comprising:

precharging channel material of strings of memory cells in both a selected sub-block and an unselected sub-block in a block of memory cells to a precharge voltage during a first portion of a programming operation; and

after precharging the channel material of the strings of memory cells in the selected sub-block and the unselected sub-block, applying a programming voltage to an access line of a selected memory cell in the selected sub-block of the block of memory cells during a second portion of the programing operation,

wherein the selected memory cell in the selected sub-block and an unselected memory cell in the unselected sub-block are coupled to the access line, and

wherein during the second portion of the programing operation, the channel material in the unselected sub-block is charged to a first voltage higher than the precharge voltage in response to a coupled voltage induced on the channel material by the programming voltage on the selected access line of the selected memory cell in the selected sub-block.

2. The method of claim 1 , wherein the precharging further comprises enabling a select gate of a string of memory cells in the unselected sub-block to couple the precharge voltage to the channel material of the string of memory cells in the unselected sub-block.

3. The method of claim 1 , further comprising allowing the channel material of the string of memory cells in the unselected sub-block to float during the second portion of the programming operation.

4. The method of claim 3 , wherein allowing the channel material of the string of memory cells in the unselected sub-block to float comprises grounding a select line coupled to a select gate of the string of memory cells in the unselected sub-block.

5. The method of claim 1 , further comprising applying a program enable voltage to a data line during the programming operation, wherein the data line is coupled to strings of memory cells in the unselected sub-block and in the selected sub-block.

6. The method of claim 5 , wherein applying a program enable voltage to the data line comprises coupling the data line to a ground of a memory device including the block of memory cells.

7. The method of claim 6 , further comprising enabling a select gate in a string of memory cells to couple the program enable voltage to channel material of the selected memory cell during the programming operation.

8. The method of claim 1 , wherein the channel material of all of the strings of memory cells in both the selected sub-block and the unselected sub-block is precharged to the precharge voltage during the first portion of the programming operation.

9. The method of claim 1 , wherein during the second portion of the programing operation, an additional voltage risen from the precharge voltage to the first voltage charged to the channel material in the unselected sub-block is based on a coupled voltage induced by the programming voltage.

10. The method of claim 1 , while the channel material in the selected sub-block is charged to a second voltage lower than the precharge voltage.

11. The method of claim 10 , wherein during the second portion of the programing operation, the second voltage charged to the channel material in the selected sub-block is approximately 0V level.

12. An apparatus comprising:

a block of NAND memory cells comprising multiple strings of NAND memory cells, each string coupled to a data line and multiple access lines, the block of memory cells including multiple sub-blocks that may be individually selected for programming; and

a control circuit configured to identify an unselected sub-block and a selected sub-block in the block, and to cause channel material of all strings of memory cells in the unselected sub-block and the selected sub-block to be precharged to a precharge voltage during a first portion of a programming operation before applying a programming voltage on a selected memory cell in the selected sub-block during a second portion of the programming operation,

wherein during the second portion of the programing operation, the channel material in the unselected sub-block is charged to a first voltage higher than the precharge voltage in response to a coupled voltage induced on the channel material by the programming voltage on a selected access line of the selected sub-block.

13. The apparatus of claim 12 , wherein the control circuit is configured to apply the precharge voltage to the data line to precharge the unselected sub-block and the selected sub-block of the block.

14. The apparatus of claim 13 , wherein the control circuit is configured to enable a select gate of the unselected sub-block to couple the precharge voltage to the channel material of the strings of the memory cells in the unselected sub-block.

15. The apparatus of claim 13 , wherein the control circuit is configured to enable a select gate of the selected sub-block to couple the precharge voltage to the channel material of the strings of the memory cells in the selected sub-block.

16. The apparatus of claim 13 , the control circuit is configured to cause a pass voltage to be applied to the access lines of the selected sub-block and the unselected sub- block while during coupling of the precharge voltage to the channel material in the selected sub-block and the unselected sub-block.

17. The apparatus of claim 12 , wherein the control circuit is configured to cause channel material of an unselected string of the unselected sub-block to float during at least some portion of the programming operation.

18. The apparatus of claim 12 , wherein the control circuit is configured to cause a program enable voltage to be applied to the data line during the programming operation.

19. The apparatus of claim 18 , wherein the control circuit is configured to cause a select gate enabled to couple a program enable voltage to the channel material of the selected memory cell in the selected sub-block during the second portion of the programming operation.

20. The apparatus of claim 19 , wherein during the second portion of the programming operation the selected memory cell is coupled to a selected access line of the access lines, and wherein the controller is further configured to cause a pass voltage to be applied to unselected access lines during the second portion of the programming operation.

21. The apparatus of claim 12 , wherein each string of memory cells comprises memory cells at least partially surrounding a pillar of semiconductor material.

22. A method of operating a memory device, comprising:

selecting a sub-block of multiple sub-blocks within a block of multiple strings of memory cells, each string of the memory cells including a pillar of semiconductor material and being coupled to a data line and multiple access lines, the block comprising multiple sub-blocks that may be individually selected for programming, the access lines spanning two or more of the multiple sub-blocks;

during an initial part of a programming operation, precharging the pillar of each string of the multiple strings in the block by applying a precharge voltage to the pillar of each string; and

after precharging of the pillar of each string of the multiple strings in the block, applying a programming voltage to a selected memory cell in the selected sub-block during a subsequent part of the programming operation, and

wherein during the subsequent part of the programing operation, the pillar in an unselected sub-block is charged to a first voltage higher than the precharge voltage in response to a coupled voltage induced on the channel material by the programming voltage on a selected access line of the selected sub-block.

23. The method of claim 22 , wherein the selected memory cell is coupled to a same access line as an unselected memory cell in an unselected sub-block.

24. The method of claim 22 , further comprising allowing the pillar of each string of the multiple strings in the unselected sub-block to float during the subsequent part of the programming operation.