Memory device for a hierarchical memory architecture

1. A hierarchical memory device, comprising:

at least one input port; and

multiple output ports, the hierarchical memory device being configured to be simultaneously connectable in both a daisy-chain hierarchy and a hierarchical tree structure with other hierarchical memory devices, the hierarchical memory device being configured to switch traffic between the at least one input port and at least one of the multiple output ports to reduce a round-trip latency to a lowest layer of the hierarchical tree structure.

2. The hierarchical memory device of claim 1 , further comprising at least one processor core to perform multi-core memory management and autonomous computing functions, the memory management functions being configured to adjust data input/output between at least one memory interface and a buffer memory coupled to the at least one memory interface based on extracted control and operational information.

3. The hierarchical memory device of claim 2 , wherein the at least one processor is further to execute algorithms for wear leveling, caching, error detection and correction, and data manipulation to precondition sections of memory having a slower state to manage performance and reliability.

4. The hierarchical memory device of claim 2 , wherein the extracted control and operational information includes received command sets and addresses of memory devices coupled to the hierarchical memory device, the at least one processor further to interpret the received command sets and issue memory commands.

5. The hierarchical memory device of claim 2 , wherein the at least one input port and the multiple output ports are configurable by the at least one processor core.

6. The hierarchical memory device of claim 1 , further comprising a host logic interface to aggregate multiple trees within the daisy-chain hierarchy and the hierarchical tree structure.

7. The hierarchical memory device of claim 1 , further comprising a caching management block to optimize information storage locations based on access patterns.

8. The hierarchical memory device of claim 1 , further co sing a data manipulation block to invert data to increase writing performance.

9. A memory device, comprising:

at least one input port;

a number of output ports, the memory device being configured to simultaneously be connectable in both a daisy-chain hierarchy and a hierarchical tree structure with other memory devices; and

a number of interfaces having different memory formats, the number of interfaces including a NAND interface and a mass storage device interface.

10. The memory device of claim 9 , further comprising at least one processor core configured to operate the memory device as at least one type of device selected from device types including an IO mapped, a memory mapped, and a memory-mapped IO device.

11. The memory device of claim 10 , wherein the at least one processor core is further configured to interpret traffic in the daisy-chain hierarchy to determine whether the traffic is for the memory device or for a downstream/upstream node.

12. The memory device of claim 9 , wherein the at least one processor core is further configured to activate security to regulate access requests to contents of the other memory devices.

13. The memory device of claim 9 , further comprising a network interface to adjust signaling rates and receive or transmit data packet transmissions over communication links to and from the at least one memory device.

14. A hierarchical memory device, comprising:

a non-volatile memory array;

at least one input port and multiple output ports, the multiple output ports being configured to be connectable as at least one type of hierarchy selectable from hierarchies including a daisy-chain hierarchy and a hierarchical tree structure with other hierarchical memory devices; and

a memory interface configured to control communications between the non-volatile memory array and memory external to the hierarchical memory device such that the non-volatile memory array can cache data received from the external memory, the hierarchical memory device being configured to switch traffic between the at least one input port and one of the multiple output ports to reduce a round-trip latency to a lowest layer of the hierarchical tree structure.

15. The hierarchical memory device of claim 14 , further comprising a multiple bank architecture to allow splitting code and data spaces within the non-volatile memory array.

16. The hierarchical memory device of claim 14 , wherein the memory interface circuit is configured to operate selectively at increasingly higher multiples of a fundamental read rate.

17. The hierarchical memory device of claim 14 , further comprising a host interface logic device to aggregate multiple trees of the other hierarchical memory devices.

18. The hierarchical memory device of claim 17 , wherein the host interface logic device is further configured to receive addressing information from a bus coupled to the memory device and use the addressing information to access various ones of the other hierarchical memory devices.

19. The hierarchical memory device of claim 14 , further comprising a network interface to support signaling rates and data packet transmissions over communication links, the network interface the network interface being configured to support an Ethernet protocol.

20. The hierarchical memory device of claim 14 , further comprising:

storage controller logic to identify and adjust storage accesses; and

a buffer memory to program and verify processes.