Apparatuses and methods for charging a global access line prior to accessing a memory
Apparatuses and methods for charging a global access line prior to accessing a memory are described. An example apparatus may include a memory array of a memory. A plurality of global access lines may be associated with the memory array. The global access line may be charged to a ready-access voltage before any access command has been received by the memory. The global access line may be maintained at the ready-access voltage during memory access operations until the receipt of a post-access command. The post-access command may reset the global access line to an inactive voltage.
1. An apparatus comprising:
a memory array including global access lines;
voltage circuitry configured to charge at least one global access line of the global access lines to a ready-access voltage before an access command is received to access the memory array; and
a control logic circuit configured to control the voltage circuitry to charge the at least one global access line of the memory array responsive to receipt of a pre-access command, the control logic circuit configured to control the voltage circuitry based partly on a temperature condition of the memory array, the control logic circuit further configured to provide control signals that prepare the global access lines for a memory access operation.
2. An apparatus comprising:
a memory array including global access lines;
voltage circuitry configured to charge at least one global access line of the global access lines to a ready-access voltage before an access command is received to access the memory array; and
a control logic circuit configured to control the voltage circuitry to charge the at least one global access line of the memory array responsive to receipt of a pre-access command, the control logic circuit further configured to provide control signals that prepare the global access lines for a memory access operation, wherein the control signals include control signals for temperature evaluation of the memory array.
3. The apparatus of claim 2 , the control signals include control signals for voltage value determination of the memory array based on temperature evaluation feedback including temperature conditions.
4. The apparatus of claim 3 , wherein the control signals further include signals to adjust global access line voltages based on the temperature evaluation feedback.
5. An apparatus comprising:
memory array including global access lines;
voltage circuitry configured to charge at least one global access line of the global access lines to a ready-access voltage before an access command is received to access the memory array; and
a control logic circuit configured to control the voltage circuitry to charge the at least one global access line of the memory array responsive to receipt of a pre-access command, the control logic circuit further configured to provide control signals that prepare the global access lines for a memory access operation, wherein the voltage circuitry is configured to reset the global access line of the memory array to an inactive voltage responsive to receipt of a post-access command.
6. The apparatus of claim 1 , wherein the voltage circuitry is further configured to charge the global access line of the memory array to the ready-access voltage responsive to receipt of a pre-access command.
7. An apparatus comprising:
a memory array including global access lines;
a voltage generator configured to drive at least one of the global access lines to a ready-access voltage; and
a control logic circuit configured to receive a plurality of commands regarding the at least one global access line and to provide a control signal that prepares the at least one global access line for a memory access operation, the control logic circuit configured to control the voltage generator based partly on a temperature condition of the memory array.
8. The apparatus of claim 7 , wherein the control logic circuit is configured to provide the control signal to cause the at least one global access line to be charged to a ready-access voltage responsive to receipt of a command of the plurality of commands.
9. The apparatus of claim 7 , wherein the control logic circuit is configured to provide the control signal to adjust a ready-access voltage of the at least one global access line to an access voltage and to cause the memory array to be accessed using the access voltage responsive to receipt of a command of the plurality of commands.
10. The apparatus of claim 9 , wherein the command comprises a read access command.
11. The apparatus of claim 7 , wherein the control logic circuit is configured to control the voltage circuitry to charge the at least one global access line responsive to receipt of a pre-access command.
12. The apparatus of claim 11 , wherein the control logic circuit is further configured to control the voltage circuitry to charge each global access line of the global access lines, including the at least one global access line, responsive to receipt of a respective pre-access command for each global access line.
13. A method comprising:
receiving a first command;
providing a control signal that prepares a global access line of a memory for memory access;
determining a voltage for the global access line based partly on a temperature condition of the memory;
receiving a second command; and
accessing the memory responsive to receipt of the second command.
14. The method of claim 13 , further comprising:
responsive to receipt of the control signal, charging the global access line of the memory to a ready-access voltage responsive to receipt of the first command.
15. The method of claim 13 , further comprising:
responsive to receipt of the control signal, adjusting the ready-access voltage of the global access line of the memory to a different voltage.
16. A method comprising:
receiving a first command;
providing a control signal that prepares a global access line of a memory for memory access;
receiving a second command;
accessing the memory responsive to receipt of the second command; and
responsive to receipt of the control signal, resetting the global access line to an inactive voltage following the memory access.
17. The method of claim 13 , wherein receiving the second command comprises receiving a read access command and wherein accessing the memory comprises accessing the memory responsive to a control signal provided by a control logic circuitry responsive to receipt of the read access command.
18. The method of claim 13 , wherein the global access line is driven to a ready-access voltage responsive to receipt of a pre-access command.
19. A method comprising:
receiving a first command;
providing a control signal that prepares a global access line of a memory for memory access, wherein the global access line is driven to a ready-access voltage responsive to receipt of a pre-access command, wherein the global access line is driven to an adjusted voltage from the ready-access voltage based, at least in part, on temperature evaluation feedback;
receiving a second command; and
accessing the memory responsive to receipt of the second command.
20. A method comprising:
receiving a first command;
providing a control signal that prepares a global access line of a memory for memory access, wherein the global access line is driven to a ready-access voltage responsive to receipt of a pre-access command;
adjusting the ready-access voltage of the global access line based on a measured temperature of the memory;
receiving a second command; and
accessing the memory responsive to receipt of the second command.