Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
View Patent ↗Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die.
1. A system, comprising:
at least one of a processor and a memory device, wherein at least one of the processor and the memory device includes a microelectronic device comprising
a semiconductor substrate including integrated circuitry and bond-pads electrically coupled to the integrated circuitry, wherein the semiconductor substrate has a thickness of between approximately 10 to 50 microns;
through-substrate interconnects in electrical contact with corresponding bond-pads and extending completely through the semiconductor substrate to a terminus at a back side of the substrate; and
an attachment structure at the back side of the semiconductor substrate, wherein the attachment structure comprises
an at least initially flexible dielectric film having a plurality of preformed openings at least partially aligned with the portions of the through-substrate interconnects accessible at the back side of the semiconductor substrate; and
electrical couplers in the openings and in contact with the corresponding accessible portions of the through-substrate interconnects.
2. The system of claim 1 wherein the attachment structure has a thickness less than a thickness of the semiconductor substrate.
3. The system of claim 1 wherein the attachment structure comprises a single, unitary piece of dielectric film having a size and shape corresponding to a size and shape of the back side of the semiconductor substrate.
4. The system of claim 1 wherein the electrical couplers are positioned to electrically couple the through-substrate interconnects to one or more external contacts within a footprint of the semiconductor substrate.
5. The system of claim 1 wherein the dielectric film has a first side in contact with the back side the semiconductor substrate and a second side opposite the first side, and wherein external surfaces of the electrical couplers are at least approximately co-planar with the second side of the dielectric film.
6. The system of claim 1 wherein the dielectric film has a first side in contact with the back side the semiconductor substrate and a second side opposite the first side, and wherein external surfaces of the electrical couplers are not co-planar with the second side of the dielectric film.
7. The system of claim 1 wherein individual preformed openings have a first dimension larger than a second dimension of the back side portions of the corresponding through-substrate interconnects.
8. The system of claim 1 wherein the dielectric film has a thickness less than a thickness of the semiconductor substrate.
9. The system of claim 1 wherein the dielectric film comprises a single, unitary piece of adhesive film having a footprint at least approximately identical to a footprint of the semiconductor substrate.
10. The system of claim 1 wherein the dielectric film comprises a film-over-wire die attach film.
11. The system of claim 1 wherein the electrical couplers comprise one or more layers of a conductive material deposited onto the corresponding back side portions of the through-substrate interconnects.
12. The system of claim 11 wherein the conductive material comprises at least one of Cu, Ni, Au, palladium, solder, and a conductive polymer.
13. The system of claim 1 wherein the electrical couplers comprise a first layer of Cu deposited onto the corresponding back side portions of the through-substrate interconnects, a second layer of Ni deposited onto the first layer, and a third layer of Au deposited onto the second layer.
14. The system of claim 1 wherein the electrical couplers comprise a first layer of Ni deposited onto the corresponding back side portions of the through-substrate interconnects, a second layer of Au deposited onto the first layer, and a third layer of palladium deposited onto the second layer.