Methods of forming phase change memory apparatuses

1. A method of forming a phase change memory apparatus, the method comprising:

patterning an n-doped semiconductor base region of a bipolar junction transistor selector to form word lines including elongated portions in a first horizontal direction;

forming a dielectric material over base contacts for electrically connecting to the n-doped semiconductor base region and over p-doped semiconductor emitter regions of the bipolar junction transistor selector;

patterning the dielectric material to form elongated dielectric structures in a second horizontal direction transverse to the first horizontal direction; and

forming a heating element material over sidewalls of the elongated dielectric structures, the heating element material having a height in a vertical direction transverse to the first horizontal direction and the second horizontal direction, a width parallel to the second horizontal direction, and a thickness parallel to the first horizontal direction.

2. The method of claim 1 , wherein patterning the dielectric material to form elongated dielectric structures comprises aligning sidewalls of the elongated dielectric structures with the p-doped semiconductor emitter regions of the bipolar junction transistor selector.

3. The method of claim 1 , wherein patterning the dielectric material to form elongated dielectric structures comprises leaving portions of the dielectric material covering the base contacts and covering doped semiconductor regions immediately adjacent to the base contacts.

4. The method of claim 1 , further comprising forming conductive cell contacts and patterning the heating element material to form heating elements coupled to the conductive cell contacts.

5. The method of claim 4 , further comprising forming phase change memory cells over and in contact with the heating elements.

6. The method of claim 5 , wherein patterning the heating element material to form the heating elements comprises patterning the heating element material to form L-shaped heating elements including a heating element width parallel to the second horizontal direction.

7. The method of claim 6 , further comprising forming bit lines over and in electrical contact with the phase change memory cells, the bit lines including a bit line width parallel to the first horizontal direction and a bit line length, greater than the bit line width, parallel to the second horizontal direction, wherein the heating element width parallel to the second horizontal direction is less than the bit line width parallel to the first horizontal direction.

8. The method of claim 4 , wherein patterning the heating element material to form the heating elements comprises forming substantially planar vertical portions, wherein the thickness of the heating element material parallel to the first horizontal direction is less than the width of the heating element material parallel to the second horizontal direction.

9. A method of forming a phase change memory apparatus, the method comprising:

forming base contacts for electrical access to an n-doped semiconductor base region including an elongated portion in a first horizontal direction;

forming conductive cell contacts adjacent to the base contacts;

electrically coupling heating elements to some of the conductive cell contacts, without electrically coupling the heating elements to the conductive cell contacts immediately adjacent to the base contacts, wherein the heating elements include vertical portions having a thickness parallel to the first horizontal direction, a width parallel to a second horizontal direction transverse to the first horizontal direction, and a height in a vertical direction transverse to the first horizontal direction and the second horizontal direction;

forming a dielectric material over the conductive cell contacts immediately adjacent to the base contacts; and

forming phase change memory cells over and coupled to the heating elements and over the dielectric material.

10. The method of claim 9 , wherein forming the phase change memory cells comprises forming the phase change memory cells to have a width parallel to the first horizontal direction perpendicular to the second horizontal direction that is greater than the heating element width parallel to the second horizontal direction.

11. The method of claim 9 , further comprising forming bipolar junction transistor selectors coupled to the heating elements, the bipolar junction transistor selectors including the n-doped semiconductor base region and a p-doped semiconductor emitter region coupled to the n-doped semiconductor base region.

12. The method of claim 9 , further comprising forming bit lines over and electrically coupled to the phase change memory cells, the bit lines including a bit line width parallel to the first horizontal direction and a bit line length parallel to the second horizontal direction.

13. The method of claim 12 , further comprising forming the bit line width parallel to the first horizontal direction to be greater than the heating element width parallel to the second horizontal direction.

14. A method of forming a phase change memory apparatus, the method comprising:

forming an array of memory cells comprising:

forming heating elements including vertical portions having a thickness parallel to a first horizontal direction, a width parallel to a second horizontal direction transverse to the first horizontal direction, and a height in a vertical direction transverse to the first horizontal direction and the second horizontal direction, wherein the thickness of the vertical portions parallel to the first horizontal direction is less than the width of the vertical portions parallel to the second horizontal direction;

electrically coupling the heating elements to respective phase change materials of individual memory cells of the array;

forming bit lines including a bit line width parallel to the first horizontal direction and a bit line length parallel to the second horizontal direction, wherein the bit line width is less than the bit line length; and

electrically coupling the bit lines to respective aligned groups of at least some of the memory cells of the array.

15. The method of claim 14 , wherein the width of the vertical portions of the heating elements parallel to the second horizontal direction is less than the bit line width parallel to the first horizontal direction.

16. The method of claim 14 , wherein forming the heating elements further comprises:

forming the heating elements in an L-shaped configuration including horizontal portions adjoining the vertical portions; and

forming a dielectric material at least partially disposed between the horizontal portions and the vertical portions of the heating elements.

17. The method of claim 14 , further comprising forming bipolar junction transistor selectors, comprising:

forming a common p-doped semiconductor collector region including elongated portions parallel to the first horizontal direction;

forming n-doped semiconductor base regions over the p-doped semiconductor collector region; and

forming p-doped semiconductor emitters between the n-doped semiconductor base regions and respective individual heating elements of the array of memory cells.

18. The method of claim 17 , further comprising forming conductive cell contacts between the p-doped semiconductor emitters of the bipolar junction transistor selectors and respective individual heating elements of the array of memory cells, the conductive cell contacts coupled to the respective individual heating elements.

19. The method of claim 17 , further comprising:

electrically coupling base contacts to respective n-doped semiconductor base regions of respective bipolar junction transistor selectors to form base contact columns; and

forming dummy memory cells immediately adjacent to the base contact columns, the dummy memory cells comprising a phase change memory material, wherein no heating elements are in physical contact with the phase change memory material of the dummy memory cells.

20. The method of claim 17 , wherein forming the n-doped semiconductor base regions comprises patterning the n-doped semiconductor base regions to form word lines including elongated portions parallel to the first horizontal direction.