Element value comparison in memory

1. An apparatus, comprising:

a first group of memory cells coupled to a sense line and to a number of first access lines;

a second group of memory cells coupled to the sense line and to a number of second access lines; and

a controller configured to operate sensing circuitry to compare a value of a first element stored in the first group of memory cells to a value of a second element stored in the second group of memory cells to determine which of the value of the first element and the value of the second element is greater;

wherein the comparison comprises comparing the value of the first element to the value of the second element on a bit-by-bit basis.

2. The apparatus of claim 1 , wherein the controller configured to operate the sensing circuitry to perform the number of operations comprises the controller configured to operate sensing circuitry to perform at least one of a number of AND operations, OR operations, and INVERT operations without performing a sense line address access.

3. The apparatus of claim 2 , wherein the sensing circuitry comprises a number of sense amplifiers and a number of compute components.

4. The apparatus of claim 3 , wherein each of the number of compute components comprises a number of transistors formed on pitch with memory cells corresponding to a particular one of a number of columns of memory cells.

5. The apparatus of claim 1 , wherein a data value that indicates whether the value of the first element is greater than the second element is stored in a memory cell coupled to a second sense line and an access line other than the number of first access lines and other than the number of second access lines.

6. A method for performing an element comparison, comprising:

performing, using sensing circuitry, an element comparison operation on:

a first element stored in a first group of memory cells coupled to a sense line and to a first number of access lines of a memory array; and

a second element stored in a second group of memory cells coupled to the sense line and to a number of second access lines of the memory array; and

determining whether a value of the first element is greater than a value of the second element;

wherein performing the element comparison operation comprises comparing a data unit in a first data unit position of the first element to a data unit in the first data unit position of the second element.

7. The method of claim 6 , wherein comparing the data units comprises comparing a least significant data unit of the first element to a least significant data unit of the second element.

8. The method of claim 6 , wherein performing the element comparison operation comprises comparing each data unit of the first element in a respective data unit position to a data unit in a same respective data unit position of the second element.

9. An apparatus comprising:

a first group of memory cells coupled to a number of sense lines and to a number of first access lines;

a second group of memory cells coupled to the number of sense lines and to a number of second access lines; and

a controller configured to:

perform, using sensing circuitry, a plurality of greater vector determination operations, in parallel, by comparing a plurality of first elements stored as bit-vectors in the first group of memory cells to a plurality of second elements stored as bit-vectors in the second group of memory cells; and

cause a plurality of results of the respective plurality of greater vector determination operations to be stored in a third group of memory cells coupled to a number of third access lines.

10. The apparatus of claim 9 , wherein the controller is configured to use sensing circuitry to compare each of the plurality of first elements stored in memory cells coupled to a particular sense line to a respective one of the plurality of second elements that are stored in memory cells coupled to a same particular sense line.

11. The apparatus of claim 9 , wherein the controller is configured to use sensing circuitry to compare a first of the plurality of first elements to a first of the plurality of second elements, and wherein:

the first of the plurality of first elements is stored in memory cells coupled to a first of the number of sense lines and to a first group of the number of first access lines; and

the first of the plurality of second elements is in memory cells coupled to the first of the number of sense lines and to a first group of the number of second access lines.

12. The apparatus of claim 11 , wherein the controller is configured to use sensing circuitry to compare a second of the plurality of first elements to a second of the plurality of second elements, and wherein:

the second of the plurality of first elements is stored in memory cells coupled to a second of the number of sense lines and to the first group of the number of first access lines; and

the second of the plurality of second elements is in memory cells coupled to the second of the number of sense lines and to the first group of the number of second access lines.

13. The apparatus of claim 9 , wherein the controller is further configured to use sensing circuitry to compare a plurality of first elements to a plurality of second elements by:

performing an AND operation on:

a particular data unit of one of the plurality of first elements; and

an inverse of a result of performing an AND operation on the particular data unit of the one of the plurality of first elements and a particular data unit of one of the plurality of second elements.

14. The apparatus of claim 13 , wherein the controller is further configured to use sensing circuitry to compare a plurality of first elements to a plurality of second elements by:

performing an AND operation on:

the particular data unit of the one of the plurality of second elements; and

an inverse of a result of performing an AND operation on the particular data unit of the one of the plurality of first elements and the particular data unit of one of the plurality of second elements.

15. A method for performing an element comparison comprising:

performing a plurality of greater vector operations in parallel on:

a plurality (M) of first elements stored in a first group of memory cells coupled to a number of sense lines and to a number of first access lines; and

a plurality (M) of second elements stored in a second group of memory cells coupled to the number of sense lines and to a number of second access lines;

wherein the plurality of greater vector operations are performed by performing a number of operations; and

storing, in parallel, a plurality of results of the greater vector operations in a third group of memory cells coupled to the number of sense lines and to a number of third access lines.

16. The method of claim 15 , wherein performing the number of operations comprises performing at least one of a number of AND operations, OR operations, and SHIFT operations without performing a sense line address access.

17. The method of claim 15 , wherein the plurality of results each indicate whether a value of one of the plurality of first elements is greater than a value of one of the plurality of second elements.

18. The method of claim 17 , wherein the plurality of results are each associated with a comparison of an element of the plurality of first elements stored in memory cells coupled to a particular sense line and an element of the plurality of second elements stored in memory cells coupled to the particular sense line.

19. The method of claim 1 , wherein each of the plurality of first elements includes N bits and each of the plurality of second elements includes N bits.

20. The method of claim 19 , wherein:

each of the N bits of the M first elements and the N bits of the M second elements are associated with an index of N number of indexes; and

the greater vector operations are performed on a bit of an element of the M first elements with a particular index and on a bit of an element of the M second elements with the particular index.

21. The method of claim 20 , further comprising performing the greater vector operations on a bit-by-bit basis, wherein a number of iterations of performing the greater vector operations is equal to N.