IP Library Granted Patent US 10,153,254
Granted Patent B2
US 10,153,254 · App. 15/419,913 · Granted Dec 11, 2018

Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,153,254
App. No.
15/419,913
Granted
Dec 11, 2018
Kind
B2
Abstract

A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made between the first die and the first substrate, between the second die and the second substrate, and between the first and second substrates, e.g., via wire bonding. The electrical connecting elements are advantageously encased in a molding compound. Exposed contacts on the first and/or second substrates, not covered by the molding compound, provide for electrical connections between the package, and another package stacked onto the package. The package may avoid coplanarity factors, can be manufactured using existing equipment, allows for intermediate testing, and can also offer a thinner package height.

Claims (12)

1. A stackable multi-electronic die package, comprising:

a first die on a first substrate;

a second substrate on a second die;

a spacer between the first and second dies;

a first adhesive attaching the first die to the spacer;

a second adhesive attaching the second die to the spacer;

a first set of wires connecting the first die to the first substrate; and

a second set of wires connecting the second substrate to the first substrate.

2. The stackable multi-electronic die package of claim 1 further comprising a third set of wires connecting the second die to the second substrate via an opening in the second substrate.

3. The stackable multi-electronic die package of claim 1 wherein the first die and first substrate comprise a chip-on-board package construction and the second die and the second substrate comprise a board-on-chip package construction.

4. The stackable multi-electronic die package of claim 1 with the first substrate larger than the second substrate.

5. The stackable multi-electronic die package of claim 1 , wherein the spacer comprises an epoxy pad.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050702/0451 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 4 TO PATENT SECURITY AGREEMENT Recorded May 4, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042405/0909 →