Memory devices and methods which may facilitate tensor memory access with memory maps based on memory operations
Examples described herein include systems and methods which include an apparatus comprising a memory array including a plurality of memory cells and a memory controller coupled to the memory array. The memory controller comprises a memory mapper configured to configure a memory map on the basis of a memory command associated with a memory access operation. The memory map comprises a specific sequence of memory access instructions to access at least one memory cell of the memory array. For example, the specific sequence of memory access instructions for a diagonal memory command comprises a sequence of memory access instructions that each access a memory cell along a diagonal of the memory array.
1. An apparatus comprising:
a memory array comprising a plurality of memory cells; and
a memory controller coupled to the memory array, the memory controller comprising:
a memory mapper configured to configure a first memory map based on a first memory command having a first matrix operation order and associated with a first memory access operation, wherein the first memory map comprises a specific sequence of memory access instructions to access at least one memory cell of the memory array; and
an address translator configured to translate the first memory map to a second memory map based on a second matrix operation order of a second memory command associated with a second memory access operation, the second matrix operation order being different than the first matrix operation order, and further configured to identify, in the first memory map, a plurality of memory addresses of the first memory map arranged in accordance with the first matrix operation order and allocate the identified plurality of memory addresses into the second memory map in accordance with the second matrix operation order of the second memory command.
2. The apparatus of claim 1 , wherein the memory access instructions are specific to a type of memory command.
3. The apparatus of claim 1 , wherein the first memory command comprises a diagonal memory command and the second memory command comprises a determinant memory command, wherein the first matrix operation order corresponds to a diagonal operation order, and wherein the second matrix operation order corresponds to a determinant operation order.
4. The apparatus of claim 1 , wherein each memory access instruction of the specific sequence of memory access instructions comprises an instruction for a respective address of a memory cell of the plurality of memory cells.
5. The apparatus of claim 1 , wherein the memory controller is implemented in a processor.
6. The apparatus of claim 1 , wherein the memory controller is configured to receive the memory command via a bus coupled to a network interface configured to communicate with a cloud computing network.
7. The apparatus of claim 1 , further comprising:
a memory interface coupled to the memory controller and configured to communicate with the memory array.
8. The apparatus of claim 7 , wherein the memory mapper is configured to provide the first memory map to the memory array via the memory interface.
9. The apparatus of claim 7 , wherein the memory interface comprises a plurality of terminals, wherein at least one port of the plurality of terminals is configured to receive at least one of a memory command signal, an address signal, a clock signal, or a data signal.
10. The apparatus of claim 1 , wherein the second memory access operation is provided the second memory map.
11. The apparatus of claim 1 , further comprising:
another memory array comprising another plurality of memory cells, wherein the memory controller is coupled to the other memory array, wherein the specific sequence of memory access instructions comprises instructions to access at least one memory cell of the memory array and at least one memory cell of the other memory array.
12. The apparatus of claim 1 , wherein the memory command comprises a diagonal memory command, and wherein the specific sequence of memory access instructions to access at least one memory cell of the memory array comprises a sequence of memory access instructions that each access a memory cell along a diagonal of the memory array.
13. The apparatus of claim 1 , wherein the specific sequence of memory access instructions to access at least one memory cell of the memory array comprises a sequence of memory access instructions defined by the first matrix operation order of the memory command.
14. The apparatus of claim 1 , wherein the first matrix operation order of the first memory command corresponds to a matrix operation order defined by a diagonal memory command, and wherein the second matrix operation order of the second memory command corresponds to a matrix operation order defined by a determinant operation.
15. A method comprising:
obtaining a first memory command associated with a first memory access operation having a diagonal operation order;
retrieving a first memory map for the first memory access operation based at least on the first memory command;
performing the first memory access operation based on the first memory map;
obtaining a second memory command associated with a second memory access operation;
translating the first memory map to a second memory map for the second memory access operation in accordance with the second memory access operation having a determinant operation order;
identifying, in the first memory map, a plurality of memory addresses of the first memory map arranged in accordance with the diagonal operation order; and
allocating the identified plurality of memory addresses into the second memory map in accordance with the determinant operation order of the second memory command.
16. The method of claim 15 , wherein the first memory map comprises a specific sequence of memory access instructions to access a plurality of memory cells.
17. The method of claim 16 , wherein performing the first memory access operation based on the first memory map comprises accessing respective addresses of the plurality of memory cells based on the first memory map.
18. The method of claim 15 , wherein the first memory map is based on the diagonal operation order of the first memory access operation.
19. A method comprising:
obtaining a first memory command associated with a first memory access operation;
obtaining a second memory command associated with a second memory access operation;
determining that the second memory access operation is for use in a second matrix operation order different than a first matrix operation order for use in the first memory access operation;
translating a first memory map of the first memory command to a second memory map of the second memory command based on the determination regarding the second matrix operation order being different than the first matrix operation order, wherein translating the first memory map of the first memory command to the second memory map of the second memory command comprises:
identifying, in the first memory map, a plurality of memory addresses of the first memory map arranged in accordance with the first matrix operation order; and
allocating the identified plurality of memory addresses into the second memory map in accordance with the second matrix operation order of the second memory command; and
providing the second memory map to perform the second memory access operation.
20. The method of claim 19 , wherein the first memory map is based on the first matrix operation order of the first memory command that was provided to perform the first memory access operation.
21. The method of claim 19 , further comprising:
accessing a plurality of memory cells based on the second memory map.