Self-aligned cross-point phase change memory-switch array
Subject matter disclosed herein relates to a memory device, and more particularly to a self-aligned cross-point phase change memory-switch array and methods of fabricating same.
1. A memory device comprising:
a plurality of memory structures, each memory structure of the plurality of memory structures comprising a phase change memory layer between a first memory electrode layer and a second memory electrode layer, and the phase change memory layer and the second memory electrode layer being isolated from neighboring memory structures in a first direction and a second direction, wherein the first memory electrode layer has a same width as an electrically conductive line of a first plurality of electrically conductive lines extending in the first direction, and wherein the electrically conductive line directly contacts the first memory electrode layer; and
a plurality of switch structures over the plurality of memory structures, each switch structure of the plurality of switch structures comprising a switch layer that comprises a chalcogenide material and is isolated from neighboring switch structures in the first direction and the second direction, wherein the switch layer has a same width as the electrically conductive line of the first plurality of electrically conductive lines extending in the first direction.
2. The memory device of claim 1 , wherein each of the memory structures is in series with a corresponding one of the switch structures to each form one of a plurality of memory cells.
3. The memory device of claim 2 , further comprising:
the first plurality of electrically conductive lines located under the plurality of memory structures; and
a second plurality of electrically conductive lines located over the plurality of switch structures,
wherein the first plurality of electrically conductive lines and the second plurality of electrically conductive lines interconnect the plurality of memory cells of the memory device and comprise a different material than the first memory electrode layer or the second memory electrode layer.
4. The memory device of claim 1 , wherein each switch structure of the plurality of switch structures further comprises a first switch electrode layer and a second switch electrode layer, and wherein the switch layer is between the first switch electrode layer and the second switch electrode layer.
5. The memory device of claim 4 , wherein the first switch electrode layer is in contact with the second memory electrode layer.
6. The memory device of claim 4 , wherein the first switch electrode layer extends between two or more neighboring switch structures.
7. The memory device of claim 4 wherein the first plurality of electrically conductive lines is in contact with the first memory electrode layer and a second plurality of electrically conductive lines is in contact with the second switch electrode layer.
8. The memory device of claim 1 , wherein the first memory electrode layer and the second memory electrode layer comprise titanium nitride (TiN), carbon, or both.
9. A memory device comprising:
a plurality of memory cells, each memory cell including a switch structure located in series with a memory structure, wherein:
each switch structure comprises a switch layer that comprises a chalcogenide material and is isolated from switch layers of other switch structures of one or more memory cells in a first direction and a second direction; and
each memory structure comprises a phase change memory layer between a first memory electrode layer and a second memory electrode layer, and the phase change memory layer and the first memory electrode layer being isolated from the one or more memory cells in the first direction and the second direction;
a first plurality of electrically conductive lines extending in the first direction and coupled with a plurality of switch structures; and
a second plurality of electrically conductive lines extending in the second direction and coupled with a plurality of memory structures, wherein the first plurality of electrically conductive lines and the second plurality of electrically conductive lines interconnect the plurality of memory cells, wherein the second memory electrode layer has a same width as an electrically conductive line of the second plurality of electrically conductive lines, wherein the switch layer has a same width as the electrically conductive line of the second plurality of electrically conductive lines, and wherein the electrically conductive line directly contacts the second memory electrode layer.
10. The memory device of claim 9 , further comprising:
a memory controller coupled with the first plurality of electrically conductive lines and the second plurality of electrically conductive lines.
11. The memory device of claim 9 , wherein each of the plurality of switch structures further comprise a first switch electrode layer and a second switch electrode layer, and wherein the switch layer is between the first switch electrode layer and the second switch electrode layer.
12. The memory device of claim 11 , wherein the first switch electrode layer extends between two or more switch structures.
13. The memory device of claim 12 , wherein the first plurality of electrically conductive lines are formed of a different material than the first memory electrode layer, the second memory electrode layer, or both.