Writing to cross-point non-volatile memory
View Patent ↗Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. Following an access operation (e.g., a read or write operation) of a target memory cell, untargeted memory cells may be discharged by applying a discharge voltage to the common conductive line. The discharge voltage may, for example, have a polarity opposite to the access voltage. In other examples, a delay may be instituted between access attempts in order to discharge the untargeted memory cells.
1. An apparatus, comprising:
a ferroelectric memory cell positioned between a first conductive line and a second conductive line; and
a controller in electronic communication with the first conductive line and the second conductive line, wherein the controller is operable to:
apply an access voltage to the ferroelectric memory cell via the first conductive line and the second conductive line during an access operation; and
apply a first discharge voltage to the ferroelectric memory cell via the first conductive line and the second conductive line following applying the access voltage.
2. The apparatus of claim 1 , further comprising a selection component, wherein an amplitude of the access voltage is greater than a threshold voltage of the selection component, wherein a polarity of the first discharge voltage is different from a polarity of the access voltage, and wherein an amplitude of the first discharge voltage is less than the threshold voltage of the selection component.
3. The apparatus of claim 2 , wherein the controller is operable to:
apply a second discharge voltage to the ferroelectric memory cell following applying the first discharge voltage, wherein a polarity of the second discharge voltage is different from the polarity of the access voltage, and wherein an amplitude of the second discharge voltage is less than the threshold voltage of the selection component.
4. The apparatus of claim 1 , further comprising a counter, wherein the controller is operable to:
increment a value of the counter based at least in part on applying the access voltage.
5. The apparatus of claim 4 , wherein the controller is operable to:
apply the first discharge voltage based at least in part on the value of the counter exceeding a threshold.
6. The apparatus of claim 5 , wherein the controller is operable to:
reset the value of the counter based at least in part on the value of the counter exceeding the threshold.
7. The apparatus of claim 5 , wherein the controller is operable to:
identify the threshold based at least in part on a rate of access attempts associated with the ferroelectric memory cell.
8. An apparatus, comprising:
a first ferroelectric memory cell;
a second ferroelectric memory cell in electronic communication with the first ferroelectric memory cell; and
a controller in electronic communication with the first ferroelectric memory cell and the second ferroelectric memory cell, wherein the controller is operable to:
perform a first access operation for the first ferroelectric memory cell;
set a value of a monitoring device based at least in part on performing the first access operation; and
perform a second access operation for the second ferroelectric memory cell based at least in part on the value of the monitoring device.
9. The apparatus of claim 8 , wherein the controller is operable to:
identify a discharge rate of the first ferroelectric memory cell, and wherein the controller is operable to perform the second access operation based at least in part on the value of the monitoring device satisfying a threshold associated with the discharge rate.
10. The apparatus of claim 8 , wherein the monitoring device comprises a timer, and wherein the controller is operable to:
start the timer based at least in part on performing the first access operation.
11. The apparatus of claim 8 , wherein the monitoring device comprises a timer, and wherein the controller is operable to:
perform the second access operation based on the value of the timer exceeding a threshold.
12. The apparatus of claim 11 , wherein the controller is operable to:
reset the timer based at least in part on performing the second access operation.
13. The apparatus of claim 11 , wherein the controller is operable to:
access a third ferroelectric memory cell that is isolated from the first ferroelectric memory cell before the timer exceeds the threshold.
14. The apparatus of claim 8 , wherein the monitoring device comprises a count-down timer, and wherein the controller is operable to:
perform the second access operation based at least in part on an expiration of the count-down timer.
15. An apparatus, comprising:
a ferroelectric memory cell;
a first conductive line in electronic communication with the ferroelectric memory cell;
a second conductive line in electronic communication with the ferroelectric memory cell;
a biasing component configured to apply an access voltage to the ferroelectric memory cell via the first and second conductive lines; and
a counter in electronic communication with the first conductive line, the second conductive line, and the biasing component, the counter configured to increment a value based at least in part on the biasing component applying the access voltage to the ferroelectric memory cell.
16. The apparatus of claim 15 , further comprising:
a memory controller, wherein the memory controller comprises the counter.
17. The apparatus of claim 15 , further comprising:
a pillar in contact with the first and second conductive lines, wherein the pillar comprises a first electrode, a selection component, and the ferroelectric memory cell, wherein the ferroelectric memory cell comprises a second electrode, a ferroelectric memory element, and a third electrode.
18. The apparatus of claim 15 , further comprising:
a voltage regulator in electronic communication with the biasing component.
19. The apparatus of claim 15 , wherein the counter comprises a timer, the timer being configured to start based at least in part on the biasing component applying the access voltage to the ferroelectric memory cell.
20. The apparatus of claim 19 , wherein the timer comprises a count-up timer, a count-down timer, or both.