IP Library Granted Patent US 10,134,798
Granted Patent B2
US 10,134,798 · App. 15/284,232 · Granted Nov 20, 2018

Pixel with strained silicon layer for improving carrier mobility and blue response in imagers

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Quick Facts
Patent No.
US 10,134,798
App. No.
15/284,232
Granted
Nov 20, 2018
Kind
B2
Abstract

An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag, and improves blue response in imaging devices.

Claims (18)

1. A system comprising:

a plurality of pixel cells, wherein at least one of the pixel cells comprises:

a semiconductor substrate including a strained silicon layer at an upper portion of the semiconductor substrate, and

a photosensor for generating charge formed in an upper region of the semiconductor substrate, wherein the photosensor comprises a photosensitive region buried at least in part within the semiconductor substrate and separated from the strained silicon layer by an intermediary portion of the semiconductor substrate; and

a readout circuit formed on the semiconductor substrate and comprising at least one output transistor.

2. The system of claim 1 , wherein—

the at least one of the pixel cells further comprises a floating diffusion region; and

the at least one output transistor is a reset transistor connected to the floating diffusion region for resetting the charge on the floating diffusion region.

3. The system of claim 2 , wherein the readout circuit further comprises:

a transfer transistor connected to the photosensor and the floating diffusion region for transferring charge from the photosensor to the floating diffusion region,

a source-follower transistor having a gate for receiving charge from the floating diffusion region, and

a row select transistor connected to the source-follower transistor for outputting a signal produced by the source-follower transistor.

4. The system of claim 1 , wherein the intermediary portion comprises an undoped portion of the semiconductor substrate.

5. The system of claim 1 , wherein the photosensor is buried entirely below the strained silicon layer.

6. The system of claim 1 , wherein the strained silicon layer has a thickness of about 500 Å to about 1000 Å.

7. The system of claim 1 , wherein the strained silicon layer comprises a top silicon layer formed over a silicon-germanium layer.

8. The system of claim 7 , wherein the silicon-germanium layer is graded.

9. The system of claim 7 , wherein the silicon-germanium layer has a germanium concentration of about 30% to about 40%.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050702/0451 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 4 TO PATENT SECURITY AGREEMENT Recorded May 4, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042405/0909 →