IP Library Granted Patent US 10,734,581
Granted Patent B2
US 10,734,581 · App. 15/423,965 · Granted Aug 4, 2020

Memory cell structures

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,734,581
App. No.
15/423,965
Granted
Aug 4, 2020
Kind
B2
Abstract

The present disclosure includes memory cell structures and method of forming the same. One such method includes forming a memory cell includes forming, in a first direction, a select device stack including a select device formed between a first electrode and a second electrode; forming, in a second direction, a plurality of sacrificial material lines over the select device stack to form a via; forming a programmable material stack within the via; and removing the plurality of sacrificial material lines and etching through a portion of the select device stack to isolate the select device.

Claims (30)

1. A method of forming a memory cell, comprising:

forming a plurality of stack structures in a length direction parallel to one another, and separated from each other in a first direction perpendicular to the length direction, wherein each one of the plurality of stack structures comprises:

plural select device stacks; and

a dielectric material comprising plural segments, wherein forming the plurality of stack structures comprises:

forming openings in the plural select device stacks in the length direction and forming the dielectric material within the openings;

subsequent to forming the plurality of stack structures, forming a plurality of sacrificial material lines in a direction perpendicular to the length direction and over the plural select device stacks and the dielectric material to form trenches;

subsequent to formation of the plurality of sacrificial material lines and the formation of the trenches, forming a programmable material in each of the trenches, the trenches extending in the length direction and including a bottom and sidewalls,

wherein the programmable material contacts at least a portion of a sacrificial material line, the dielectric material and an electrode material of the plural select device stacks;

subsequent to the formation of the programmable material in each of the trenches, forming on the programmable material and within the trench, a different electrode material extending in the length direction; and

subsequent to the formation of the different electrode material, removing the plurality of sacrificial material lines.

2. The method of claim 1 , wherein forming the programmable material comprises forming the programmable material via a damascene process.

3. The method of claim 1 , wherein forming the plurality of stack structures comprises forming at least one of a metal-semiconductor-metal (MSM) stack structure, a metal-insulator-metal (MIM) stack structure, and a conductor-semiconductor-conductor (CSC) stack structure.

4. The method of claim 1 , wherein forming the programmable material comprises forming at least one of resistive random access memory (RRAM) material, conductive bridging random access memory (CBRAM) material, phase-change random access memory (PCRAM) material, and/or spin-transfer-torque random access memory (STT-RAM) material.

5. The method of claim 1 , wherein forming the programmable material and forming the different electrode material comprises forming a plurality of programmable material cell stack structures via a damascene process.

6. The method of claim 1 , further comprising:

subsequent to removal of the plurality of sacrificial material lines, removing a portion of each of the plural select device stacks to isolate a select device of each of the plural select device stacks.

7. A method of forming a memory cell, comprising:

forming a first stack structure comprising a first electrode material over a substrate material, a non-ohmic select device material over the first electrode material, and a second electrode material over the non-ohmic select device material;

forming openings in the first stack structure in a first direction and forming a dielectric material within the openings;

subsequent to forming the dielectric material within the openings, forming a sacrificial material over the second electrode material and the dielectric material, the sacrificial material contacting the second electrode and the dielectric material;

subsequent to forming the sacrificial material, forming a second stack structure comprising a programmable material contacting the second electrode and the dielectric material within a trench formed by the sacrificial material formation,

wherein the programmable material contacts at least a portion of the sacrificial material;

exhuming a portion of the sacrificial material subsequent to forming the second stack structure; and

subsequent to exhuming the portion of the sacrificial material, etching through a portion of the first stack structure to isolate the non-ohmic select device material.

8. The method of claim 7 , wherein etching through a portion of the first stack structure comprises etching through the first electrode material to isolate the non-ohmic select device material.

9. The method of claim 7 , wherein etching through a portion of the first stack structure comprises etching through the first electrode material, the non-ohmic select device material, and the second electrode material to isolate the non-ohmic select device material.

10. The method of claim 7 , comprising forming a third electrode over the second stack structure.

11. The method of claim 7 , wherein exhuming a portion of the sacrificial material comprises exhuming a plurality of carbon material sacrificial material lines.

12. The method of claim 7 , wherein exhuming a portion of the sacrificial material comprises removing a plurality of sacrificial material lines utilizing an oxygen plasma material.

13. The method of claim 7 , wherein forming the second stack structure comprises forming the programmable material via a damascene process.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050702/0451 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 4 TO PATENT SECURITY AGREEMENT Recorded May 4, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042405/0909 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2017
From: SILLS, SCOTT E.; RAMASWAMY, D.V. NIRMAL
To: MICRON TECHNOLOGY, INC.
Reel/Frame 041167/0540 →