Selective error rate information for multidimensional memory
A memory device can include three-dimensional memory entities each including a plurality of two-dimensional memory entities. A controller can read data from the memory at a first resolution and collect error rate information from the memory at a second resolution including a portion of a two-dimensional memory entity. The controller can determine a quantity of two-dimensional memory entities that have a greater error rate than a remainder of the two-dimensional memory entities based on the error rate information. The controller can determine a quantity of portions of three-dimensional memory entities that have a greater error rate than a remainder of the portions of three-dimensional memory entities based on the error rate information excluding error rate information for portions of the two-dimensional memory entities associated with the quantity of two-dimensional memory entities. The controller can cull the quantity of the two-dimensional memory entities and the quantity of the three-dimensional memory entities.
1. A memory apparatus, comprising:
a memory device including three-dimensional memory entities each comprising a plurality of two-dimensional memory entities; and
a controller coupled to the memory device, wherein the controller is configured to:
read data from the memory device at a first resolution;
collect error rate information from the memory device at a second resolution comprising a portion of a two-dimensional memory entity;
determine a quantity of two-dimensional memory entities that have a greater error rate than a remainder of the two-dimensional memory entities based on the error rate information;
determine a quantity of portions of three-dimensional memory entities that have a greater error rate than a remainder of the portions of three-dimensional memory entities based on the error rate information excluding error rate information for portions of the two-dimensional memory entities associated with the quantity of two-dimensional memory entities; and
cull the quantity of the two-dimensional memory entities and the quantity of the three-dimensional memory entities from the memory apparatus.
2. The apparatus of claim 1 , wherein the first resolution comprises a respective memory element from each two-dimensional memory entity contained within a selected three-dimensional memory entity.
3. The apparatus of claim 1 , wherein the portions of the three-dimensional memory entities include the portions of the two-dimensional memory entities therein.
4. The apparatus of claim 1 , wherein two-dimensional memory entities and three-dimensional memory entities each contain a plurality of memory elements; and
wherein the error information comprises raw bit error rate information.
5. A method, comprising:
collecting error rate information for a memory apparatus at a sub-tile resolution, wherein:
the memory apparatus includes memory elements,
the memory elements are arranged in tiles, where sub-tiles are portions of the tiles, and
the tiles are aggregated into slices, where sub-slices are portions of the slices,
determining a quantity of the tiles that have a greater error rate than a remainder of the tiles based on the error rate information;
determining a quantity of the sub-slices that have a greater error rate than a remainder of the sub-slices based on the error rate information excluding error rate information for sub-tiles associated with the quantity of tiles; and
culling the quantity of the tiles and the quantity of the sub-slices from the memory apparatus.
6. The method of claim 5 , further comprising:
provisioning a predefined quantity of spare tiles; and
substituting, for a particular page of data, a bit from a particular spare tile for a bit from one of the remainder of tiles.
7. The method of claim 6 , further comprising substituting, for a different page of data, a bit from a different spare tile for a bit from one of the remainder of sub-slices.
8. The method of claim 6 , further comprising substituting, for a different page of data, a bit from the particular spare tile for a bit from one of the remainder of sub-slices.
9. The method of claim 6 , wherein substituting the bit from the particular spare tile for a read operation comprises overlaying the bit from the particular spare tile onto the bit from the one of the remainder of tiles in a codeword before error correction is performed on the codeword.
10. The method of claim 9 , wherein substituting the bit from the particular spare tile for a write operation comprises mirroring the bit from the one of the remainder of tiles to the particular spare tile.
11. The method of claim 5 , further comprising storing the error rate information in a table,
wherein each entry in the table comprises an error rate for a respective sub-tile;
wherein columns represent tiles of the memory apparatus; and
wherein rows represent sub-slices of the memory apparatus.
12. The method of claim 11 , further comprising:
summing the entries by column, wherein determining the quantity of the tiles comprises determining a quantity of the columns having a greater error rate than a remainder of the columns; and
summing the entries by row, excluding entries from the quantity of columns, wherein determining the quantity of sub-slices comprises determining a quantity of the rows having a greater error rate than a remainder of the rows.
13. The method of claim 5 , wherein culling comprises designating the quantity of tiles and the quantity of sub-slices as unusable portions of the memory apparatus.
14. The method of claim 5 , further comprising accessing data from the memory apparatus as pages of data, wherein each respective page of data includes one bit from each tile in a respective slice.
15. A memory apparatus, comprising:
a memory device including memory elements arranged in tiles, wherein sub-tiles are portions of the tiles, wherein a slice is an aggregation of tiles, and wherein a sub-slice is a portion of a slice; and
a controller coupled to the memory device, wherein the controller is configured to perform error management including:
error correction coding of codewords stored in sub-slices;
tile substitution of spare tiles for known unreliable tiles;
tile exclusion for a quantity of tiles that have a greater error rate than a remainder of the tiles based on error rate information collected for sub-tiles associated with the quantity of tiles; and
sub-slice exclusion for a quantity of sub-slices that have a greater error rate than a remainder of the sub-slices based on error rate information collected for sub-tiles associated with the quantity of tiles.
16. The apparatus of claim 15 , wherein the controller is further configured to:
access the memory elements at a slice level; and
read and write data to a slice as a page of data, wherein the page of data includes one bit from each tile in a respective slice.
17. The apparatus of claim 15 , wherein individual memory elements are connected by an access line and sense line combination; and
wherein the controller is configured such that sub-tiles are not able to be substituted individually.
18. The apparatus of claim 15 , wherein the controller is configured to determine the quantity of the sub-slices based on the error rate information excluding error rate information for sub-tiles associated with the quantity of tiles.
19. A non-transitory computer readable medium storing instructions executable by a processing resource to:
collect error rate information for a memory apparatus at a sub-tile resolution;
store the error rate information as entries in a table with columns representing tiles of the memory apparatus and rows representing sub-slices of the memory apparatus;
sum the entries in each column to respective first sums;
determine a quantity of columns having greater first sums than a remainder of the columns;
sum the entries in each row, excluding entries from the quantity of columns to respective second sums;
determine a quantity of rows having greater second sums than a remainder of the rows;
cull tiles corresponding to the quantity of columns from the memory apparatus; and
cull sub-slices corresponding to the quantity of rows from the memory apparatus.
20. The medium of claim 19 , further including instructions to receive an input to set the quantity of columns and the quantity of rows.
21. The medium of claim 19 , further including instructions to receive an input to adjust the quantity of columns and the quantity of rows.
22. The medium of claim 19 , further including instructions to:
provision spare tiles of the memory apparatus prior to storing user data in the memory apparatus;
substitute one of the spare tiles for an unreliable tile; and
perform error correction coding of codewords stored in the memory apparatus.
23. The medium of claim 22 , wherein the instructions to cull tiles comprise instructions to cull tiles in response to an aggregate error rate for tiles exceeding a correction capability of the memory apparatus based on error correction coding and spare tile substitution.
24. The medium of claim 19 , further including instructions to:
sum the entries in each row to respective third sums;
determine a different quantity of rows having greater third sums than a remainder of the rows;
sum the entries in each column, excluding entries from the quantity of rows to respective fourth sums;
determine a different quantity of columns having greater fourth sums than a remainder of the columns;
cull sub-slices corresponding to the different quantity of rows from the memory apparatus; and
cull tiles corresponding to the different quantity of columns from the memory apparatus.
25. The medium of claim 24 , further including instructions to determine whether culling the quantity of columns and the quantity of rows yields a better overall reduction in error rate than culling the different quantity of rows and the different quantity of columns.