Apparatuses and methods for providing word line voltages

1. A method of driving a word line by a driver that includes a first transistor coupled between the word line and a first node and second and third transistors coupled in parallel between the word line and a voltage node, the method comprising:

activating the word line, wherein the activating the word line comprises:

rendering the first, second and third transistors conductive, non-conductive and non-conductive, respectively, wherein the first transistor is rendered conductive by supplying a gate of the first transistor with a first voltage; and

supplying the first node with an active voltage; and

deactivating the word line, wherein the deactivating the word line comprises:

changing a voltage of the first node from the active voltage to an inactive voltage;

changing a voltage of the gate of the first transistor from the first voltage to a second voltage, wherein the first transistor is kept conductive by the second voltage;

rendering the third transistor conductive during the gate of the first transistor being at the second voltage; and

rendering the first and second transistors non-conductive and conductive, respectively;

wherein the first and second transistors are rendered non-conductive and conductive, respectively, after the third transistor has been rendered conductive.

2. The method of claim 1 ,

wherein gates of the first and second transistors are configured to receive a control signal, and

wherein the changing the voltage of the gate of the first transistor from the first voltage to the second voltage comprises changing a voltage of the control signal from the first voltage to the second voltage.

3. The method of claim 1 ,

wherein the driver further includes a fourth transistor coupled between gates of the first and second transistors, the fourth transistor having a gate configured to receive a third voltage; and

wherein the changing the voltage of the gate of the first transistor from the first voltage to the second voltage is caused by self-boosting of the fourth transistor responsive to the changing the voltage of the first node from the active voltage to the inactive voltage.

4. The method of claim 1 , wherein the second voltage is lower than the first voltage.

5. The method of claim 4 , wherein the first voltage is zero and the second voltage is a negative voltage.

6. The method of claim 4 , further comprising lowering a voltage of the word line responsive to the changing the voltage of the gate of the first transistor from the first voltage to the second voltage.

7. The method of claim 4 , wherein the first transistor is a p-channel field effect transistor (pFET) and the second transistor and the third transistor are n-channel field effect transistors (nFETs).

8. An apparatus comprising:

a first transistor coupled between a word line and a first node and configured to turn on responsive to a first voltage and to a second voltage at a gate thereof, and further configured to turn off responsive to a third voltage at the gate thereof; and

a second transistor coupled between the word line and a voltage node and configured to turn off responsive to the first voltage at the gate of the first transistor and further configured to turn on responsive to the third voltage at the gate of the first transistor,

wherein the word line is configured to be active responsive, at least in part, to the first voltage at the gate of the first transistor and the first node having the active voltage,

wherein the word line is configured to be inactive responsive, at least in part, to the first node having the inactive voltage, and further to the second voltage at the gate of the first transistor at a first time, and further responsive to the third voltage at a second node configured to be coupled to the gate of the first transistor and the gate of the second transistor at a second time later than the first time; and

wherein the third voltage is provided via the second node to the gate of the first transistor and the gate of the second transistor after the second voltage is provided at the gate of the first transistor.

9. The apparatus of claim 8 ,

wherein gates of the first and second transistors are connected in common configured to receive a control signal, and

wherein a voltage of the control signal is configured to change from the first voltage to the second voltage at the first time.

10. The apparatus of claim 8 ,

wherein a driver further includes a third transistor coupled between gates of the first and second transistors, a fourth transistor having a gate configured to receive a fourth voltage; and

wherein the third transistor is configured to provide the second voltage to the gate of the first transistor responsive to the fourth voltage at the gate thereof at the first time.

11. The apparatus of claim 8 , wherein the second voltage is lower than the first voltage.

12. The apparatus of claim 11 , wherein the first voltage is zero, the second voltage is a negative voltage, and the third voltage is a positive voltage.

13. The apparatus of claim 11 , wherein a voltage of the word line is configured to decrease at the first time.

14. The apparatus of claim 8 , further comprising a third transistor coupled between the word line and the voltage node and configured to turn on between the first time and the second time.

15. An apparatus comprising a word line, comprising:

a first transistor having a drain coupled to the word line and a gate configured to receive a control signal and a source configured to receive a first phase signal, wherein the first transistor is configured to turn on responsive to the control signal having a first voltage;

a second transistor having a gate configured to receive the control signal and a drain coupled to the word line;

wherein the first phase signal is at a first level at a first time, and the gate of the first transistor is configured to receive the control signal having a second voltage lower than the first voltage at the gate of the first transistor at the first time; and

wherein the gate of the first transistor and the gate of the second transistor are configured to receive the control signal having a third voltage, and the first and second transistors are configured to turn off and on, respectively, responsive to the control signal after the gate of the first transistor is configured to receive the second voltage.

16. The apparatus of claim 15 , wherein the first transistor is a pFET and the second transistor is an nFET.

17. The apparatus of claim 15 , further comprising a third transistor between the gate of the first transistor and the gate of the second transistor, the third transistor including a gate configured to receive a negative voltage,

wherein the gate of the second transistor and a source of a fourth transistor are configured to receive a global positional signal and a drain of the third transistor is configured to provide the control signal responsive, at least in part, to the global positional signal to the gate of the first transistor.

18. The apparatus of claim 15 , further comprising a third transistor having a drain coupled to the word line and a source coupled to the source of the second transistor and to a voltage node,

wherein the third transistor is configured to receive a second phase signal, and further configured to turn on responsive to the second phase signal at a third time between the first time and the second time.

19. The apparatus of claim 15 , wherein a voltage of the word line is configured to decrease responsive to the control signal at the second voltage.

20. The apparatus of claim 15 , wherein the first voltage is zero and the second voltage is a negative voltage.