Phase interpolators and push-pull buffers
Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the output of the push-pull buffer may improve the linearity of a phase interpolator using the clock signals output from the push-pull buffers.
1. An apparatus comprising:
a first buffer configured to receive a first clock signal having a first phase from a first push-pull buffer;
a second buffer configured to receive a second clock signal having a second phase from the first push-pull buffer;
a third buffer configured to receive a third clock signal having a third phase from a second push-pull buffer;
a fourth buffer configured to receive a fourth clock signal having a fourth phase from the second push-pull buffer; and
a controller configured to selectively activate the first buffer or second buffer based on a select signal and to selectively activate the third buffer or fourth buffer based on the select signal, wherein outputs of the first, second, third, and fourth buffers are coupled together to provide an output signal.
2. The apparatus of claim 1 , wherein the first clock signal has opposite polarity to the second clock signal.
3. The apparatus of claim 1 , wherein the third clock signal has opposite polarity to the fourth clock signal.
4. The apparatus of claim 1 , further comprising:
a first programmable current mirror configured to provide a first current to the first and second buffers;
a second programmable current mirror configured to provide a second current to the first and second buffers, wherein a phase of the output signal is adjusted based on the first current;
a third programmable current mirror configured to provide a third current to the third and fourth buffers; and
a fourth programmable current mirror configured to provide a fourth current to the third and fourth buffers, wherein a phase of the output signal is adjusted based on second current.
5. The apparatus of claim 4 , wherein the controller is further configured to provide a bias signal to the first, second, third, and fourth current mirrors.
6. The apparatus of claim 5 , wherein the first, second, third, and fourth currents are adjusted responsive to the bias signal.
7. The apparatus of claim 4 , wherein the first and third programmable current mirror are P-type programmable current mirrors.
8. The apparatus of claim 4 , wherein the second and fourth programmable current mirrors are N-type programmable current mirrors.
9. The apparatus of claim 1 , wherein the first and third clock signals have a 90 degree phase difference.
10. The apparatus claim 1 , wherein the first, second, third, and fourth buffers are push-pull buffers.
11. A method comprising:
receiving, at a first buffer, a first clock signal having a first phase from a first push-pull buffer;
receiving at a second buffer a second clock signal having a second phase from the first push-pull buffer;
selecting, by a controller, the first or second clock signals;
receiving at a third buffer a third clock signal having a third phase from a second push-pull buffer;
receiving at a fourth buffer a fourth clock signal having a fourth phase from the second push pull buffer;
selecting, by the controller, the third or fourth clock signals; and
interpolating the selected first or second clock signal and the selected third or fourth clock signal to provide an output signal.
12. The method of claim 10 , wherein the first clock signal has opposite polarity to the second clock signal.
13. The method of claim 10 , wherein the third clock signal has opposite polarity to the fourth clock signal.
14. The method of claim 10 , wherein the first, second, third, and fourth buffers are push-pull buffers.
15. The method of claim 10 , further comprising:
providing a first current to the selected first or second buffer;
providing a second current to the selected third or fourth buffer; and
adjusting a phase of the output signal based, at least in part, on the first and second currents.
16. The method of claim 15 , wherein the first and second currents are adjusted responsive to a bias signal.
17. The method of claim 16 , wherein the bias signal is received from the controller.
18. The method of claim 15 , wherein the first current is provided by a first current mirror and the second current is provided by a second current mirror.
19. The method of claim 15 , further comprising:
providing a third current to the selected first or second buffer;
providing a fourth current to the selected third or fourth buffer; and
adjusting the phase of the output signal based, at least in part, on the third and fourth currents.
20. The method of claim 19 , wherein the third and fourth currents are adjusted responsive to the bias signal.