Apparatuses and methods for controlling wordlines and sense amplifiers
View Patent ↗Apparatuses and methods for controlling word lines and sense amplifiers in a semiconductor device are described. An example apparatus includes: a sub word line selection signal decoder which activates at least one of a plurality of sub word selection signals responsive to row address signals; a column segment selection signal decoder which activates at least one of a plurality of column segment signals responsive to a portion of column address signals and a portion of the row address signals; a column segment selection circuit which activates at least one of a plurality of column-subword selection signals responsive to the activated column segment signal and the activated sub word selection signal; and a sub word line driver which activates at least one of a plurality of sub word lines responsive to an activated main word line and the activated sub word selection signal.
1. An apparatus comprising a decoder circuit configured to receive control information and a plurality of input signal and further configured to provide a plurality of decoded signals,
wherein the decoder circuit is configured to, when the control information is indicative of a first state based on an additive latency enable signal and an auto precharge enabled signal, activate one of the decoded signals responsive to the plurality of input signals, and to, when the control information is indicative of a second state based on the additive latency enable signal and the auto precharge enabled signal, activate each of the plurality of decoded signals irrespective of the plurality of input signals.
2. The apparatus of claim 1 , wherein the control information is responsive to at least the additive latency enable signal.
3. The apparatus of claim 1 , wherein the control information is responsive to at least the auto precharge enabled signal.
4. The apparatus of claim 1 , wherein the control information is responsive to at least a combination of the additive latency enable signal and the auto precharge enabled signal.
5. The apparatus of claim 4 , wherein the control information is indicative of the second state when at least one of the additive latency enable signal and the auto precharge enabled signal is not asserted.
6. The apparatus of claim 5 , wherein the control information is indicative of the first state when both the additive latency enable signal and the auto precharge enabled signal are asserted.
7. The apparatus of claim 1 , wherein the plurality of input signals comprises a portion of column address signals and a portion of row address signals.
8. The apparatus of claim 1 , the apparatus further comprising:
a plurality of sub word drivers, wherein each of the sub word drivers is configured to receive a corresponding one of the plurality of decoded signals and further configured to be activated responsive, at least in part, to the corresponding one of the plurality of input signals being activated.
9. An apparatus comprising a decoder circuit configured to receive control information and a plurality of input signal and further configured to provide a plurality of decoded signals,
wherein the decoder circuit is configured to, when the control information is indicative of a first state, activate one of the decoded signals responsive to the plurality of input signals, and to, when the control information is indicative of a second state, activate each of the plurality of decoded signals irrespective of the plurality of input signals, wherein the decoder circuit comprises:
a decoding circuit configured to receive the plurality of input signals and outputting a plurality of intermediate decoded signals, further configured to activate one of the intermediate decoded signals and to deactivate remaining ones of the intermediate decoded signals responsive to the plurality of input signals; and
a gate circuit configured to receive the plurality of intermediate decoded signals, the gate circuit configured to pass the intermediate decoded signal therethrough as the plurality of decoded signals, when the control information is indicative of the first state, and further configured to activate each of the decoded signals irrespective of the plurality of intermediate decoded signals, when the control information is indicative of the second state.
10. The apparatus of claim 9 ,
wherein the apparatus further comprises a plurality of functional circuits configured to receive the plurality of decoded signals, respectively, and
wherein each of the plurality of functional circuits is configured to be activated in response, at least in part, to an associated one of the decoded signals being activated.
11. The apparatus of claim 10 ,
wherein the plurality of input signals is a set of address signals; and
wherein each of the functional circuits comprises a word line driver.
12. The apparatus of claim 11 ,
wherein the set of address signals comprises at least one row address signal and at least one column address signal.
13. The apparatus of claim 9 ,
wherein the control information is produced based on at least two control signals,
wherein the control information is indicative of the second state when at least one of the at least two control signals is at a first logic level, and
wherein the control information is indicative of the first state when each of the at least two control signals is at a second logic level.
14. An apparatus comprising a decoder circuit, the decoder circuit comprising:
a plurality of logic circuits, each logic circuit of the plurality of logic circuits configured to receive a portion of row address signals and a portion of column address signals, and the plurality of logic circuits configured to provide a plurality of first output signals comprising an active signal and a plurality of inactive signals;
a control circuit configured to be responsive to a plurality of control signals and output a control signal; and
a plurality of selector circuits, each selector circuit of the plurality of selector circuits configured to receive a corresponding one of the plurality of first output signals, the plurality of selector circuits configured to provide a plurality of second output signals comprising the active signal and the plurality of inactive signals when the control signal is at a first logic level and further configured to provide the plurality of second output signals comprising a plurality of active signals when the control signal is at a second logic level.
15. The apparatus of claim 14 , wherein the control signal includes an additive latency enable signal.
16. The apparatus of claim 14 , wherein the control signal includes an auto precharge enabled signal.
17. The apparatus of claim 14 , wherein the control signal is a combination of an additive latency enable signal and the auto precharge enabled signal.
18. The apparatus of claim 17 , wherein the control signal is set to the second logic level when at least one of the additive latency enable signal and the auto precharge enabled signal is inactive.
19. The apparatus of claim 18 , wherein the control signal is set to the first logic level when both the additive latency enable signal and the auto precharge enabled signal are active.
20. The apparatus of claim 14 , the apparatus further comprising:
a plurality of sub word drivers, each sub word driver of the plurality of sub word drivers configured to receive a corresponding second output signal of the plurality of second output signals,
wherein each sub word driver of the plurality of sub word drivers is activated responsive to the corresponding second output signal in an active state, and
wherein each sub word driver of the plurality of sub word drivers is deactivated responsive to the corresponding second output signal in an inactive state.