Apparatuses and methods for providing set and reset voltages at the same time
Apparatuses and methods are described, such as those involving driver circuits that are configured to provide reset and set voltages to different variable state material memory cells in an array at the same time. Additional apparatuses, and methods are described.
1. A memory device, comprising:
an array of memory cells arranged in rows and columns, each of the cells including:
a variable state material region;
an access transistor coupled the variable state material region; and
a driver coupled to the array of memory cells to provide three different voltages to different memory cells in the array at the same time, the three different voltages including set and reset voltages to different columns in the array at the same time.
2. The memory device of claim 1 , wherein the variable state material region includes a resistance switching material.
3. The memory device of claim 2 , wherein the variable state material region includes a unipolar variable state material.
4. The memory device of claim 2 , wherein the variable state material region includes a bipolar variable state material.
5. The memory device of claim 1 , wherein the driver is a column driver.
6. The memory device of claim 1 , wherein the set voltage is configured to operate at approximately 4 volts operate at approximately 4 volts.
7. The memory device of claim 1 , wherein the reset voltage is configured to operate at approximately 2 volts operate at approximately 2 volts.
8. The memory device of claim 1 , wherein the access transistor includes an N channel access transistor.
9. The memory device of claim 1 , wherein the access transistor includes a P channel access transistor.
10. A memory device, comprising:
an array of memory cells arranged in rows and columns, each of the cells including:
a variable state material region;
an access transistor coupled the variable state material region; and
a driver coupled to the array of memory cells to provide set, reset, and inhibit voltages to different columns in the array at the same time.
11. The memory device of claim 10 , wherein the variable state material region includes a resistance switching material.
12. The memory device of claim 11 , wherein the variable state material region includes a unipolar variable state material.
13. The memory device of claim 11 , wherein the variable state material region includes a bipolar variable state material.
14. The memory device of claim 10 , wherein the set voltage is configured to operate at approximately 4 volts.
15. The memory device of claim 14 , wherein the reset voltage is configured to operate at approximately 2 volts.
16. The memory device of claim 15 , wherein the inhibit voltage is configured to operate at approximately 3 volts.