IP Library Granted Patent US 10,014,051
Granted Patent B2
US 10,014,051 · App. 15/490,316 · Granted Jul 3, 2018

Data storage with data randomizer in multiple operating modes

Inventors: Preston A. Thomson (Boise, ID); Peiling Zhang (El Dorado Hills, CA); Junchao Chen (Singapore, SG)
Assignee: Micron Technology, Inc.
G11C11/5628G11C11/5635G11C11/5642G11C16/0458G11C16/0483
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Quick Facts
Patent No.
US 10,014,051
App. No.
15/490,316
Granted
Jul 3, 2018
Kind
B2
Abstract

Methods of operating a memory include programming a particular portion of a data state to a memory cell with a data randomizer in a first operating mode, and programming a remaining portion of the data state to the memory cell with the data randomizer in a second operating mode different than the first operating mode.

Claims (27)

1. A method of operating a memory, comprising:

programming a particular portion of a data state to a memory cell, with a data randomizer in a first operating mode at a time of programming the particular portion of the data state to the memory cell; and

programming a remaining portion of the data state to the memory cell, with the data randomizer in a second operating mode different than the first operating mode at a time of programming the remaining portion of the data state to the memory cell.

2. The method of claim 1 , wherein programming the particular portion of the data state comprises programming a particular digit position of the data state.

3. The method of claim 2 , wherein programming the remaining portion of the data state comprises programming a different digit position of the data state.

4. The method of claim 3 , wherein programming the different digit position of the data state further comprises programming each digit position of the data state other than the particular digit position.

5. The method of claim 1 , wherein programming the particular portion of the data state to the memory cell, with the data randomizer in the first operating mode at the time of programming the particular portion of the data state to the memory cell, comprises programming the particular portion of the data state to the memory cell, with the data randomizer enabled at the time of programming the particular portion of the data state to the memory cell.

6. The method of claim 1 , wherein programming the remaining portion of the data state, with the data randomizer in the second operating mode at the time of programming the remaining portion of the data state to the memory cell, comprises programming the remaining portion of the data state, with the data randomizer disabled at the time of programming the remaining portion of the data state to the memory cell.

7. A method of operating a memory, comprising:

programming a particular digit position of a data state to a memory cell, with a data randomizer enabled at a time of programming the particular digit position of the data state to the memory cell; and

programming a different digit position of the data state to the memory cell, with the data randomizer disabled at a time of programming the different digit position of the data state to the memory cell.

8. The method of claim 7 , wherein programming the particular digit position of the data state comprises programming a least significant bit of the data state.

9. The method of claim 8 , wherein programming the least significant bit of the data state comprises programming the least significant bit of the data state using user data.

10. The method of claim 8 , wherein programming the different digit position of the data state comprises programming a most significant bit of the data state.

11. The method of claim 10 , wherein programming the most significant bit of the data state comprises programming the most significant bit of the data state using uniform data having a particular value.

12. The method of claim 11 , wherein the data state is a particular data state of a plurality of data states to which the memory cell may be programmed, where each data state of the plurality of data states corresponds a respective threshold voltage range, and wherein programming the particular digit position of the data state to the memory cell, with the data randomizer enabled at the time of programming the particular digit position of the data state to the memory cell, and programming the different digit position of the data state to the memory cell, with the data randomizer disabled at the time of programming the different digit position of the data state to the memory cell, programs the memory cell to a threshold voltage within either a lowest threshold voltage range of the plurality of data states or a highest threshold voltage range of the plurality of data states.

13. The method of claim 10 , further comprising programming one or more additional digit positions of the data state.

14. A method of operating a memory, comprising:

for one or more first digit positions of a data state, programming the one or more first digit positions of the data state to a memory cell, with a data randomizer in a first operating mode at a time of programming the one or more first digit positions of the data state to the memory cell;

for one or more second digit positions of the data state, after programming the one or more first digit positions of the data state to the memory cell, with the data randomizer in the first operating mode at the time of programming the one or more first digit positions of the data state to the memory cell, programming the one or more second digit positions of the data state to the memory cell, with the data randomizer in a second operating mode different than the first operating mode at a time of programming the one or more second digit positions of the data state to the memory cell.

15. The method of claim 14 , further comprising:

for one or more third digit positions of the data state, after programming the one or more second digit positions of the data state to the memory cell, with the data randomizer in the second operating mode at the time of programming the one or more second digit positions of the data state to the memory cell, programming the one or more third digit positions of the data state to the memory cell, with the data randomizer in the first operating mode at a time of programming the one or more third digit positions of the data state to the memory cell.

16. The method of claim 14 , wherein programming the one or more first digit positions of the data state to the memory cell comprises programming only a single digit position of the data state to the memory cell, and wherein programming the one or more second digit positions of the data state to the memory cell comprises programming all remaining digit positions of the data state to the memory cell.

17. The method of claim 16 , wherein programming only the single digit position of the data state to the memory cell comprises programming user data for the single digit position of the data state to the memory cell, and wherein programming all remaining digit positions of the data state to the memory cell comprises programming respective uniform data for each digit position of all remaining digit positions to the memory cell.

18. The method of claim 17 , wherein the first operating mode of the data randomizer is an enabled operating mode and wherein the second operating mode of the data randomizer is a disabled operating mode.

19. The method of claim 14 , wherein programming the one or more first digit positions of the data state to the memory cell comprises programming the one or more first digit positions of the data state to the memory cell as part of lower page data for a page of memory cells.

20. The method of claim 19 , wherein programming the one or more second digit positions of the data state to the memory cell comprises programming the one or more second digit positions of the data state to the memory cell as part of upper page data for the page of memory cells.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050702/0451 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 4 TO PATENT SECURITY AGREEMENT Recorded May 4, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042405/0909 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 18, 2017
From: THOMSON, PRESTON A.; ZHANG, PEILING; CHEN, JUNCHAO
To: MICRON TECHNOLOGY, INC.
Reel/Frame 042045/0609 →
Priority Claims (1)
SG 10201605746R · Jul 13, 2016 · national
Continuity (1)
Related Publication 20180019014A1 · Jan 18, 2018