IP Library Granted Patent US 10,409,673
Granted Patent B2
US 10,409,673 · App. 15/414,699 · Granted Sep 10, 2019

Memory devices having differently configured blocks of memory cells

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Quick Facts
Patent No.
US 10,409,673
App. No.
15/414,699
Granted
Sep 10, 2019
Kind
B2
Abstract

A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of the plurality of blocks of memory cells in a first configuration comprising one or more groups of overhead data memory cells, to configure a second block of the plurality of blocks of memory cells in a second configuration comprising a group of user data memory cells and a group of overhead data memory cells, and to configure a third block of the plurality of blocks of memory cells in a third configuration comprising only a group of user data memory cells. The group of overhead data memory cells of the second block of memory cells has a different storage capacity than at least one group of overhead data memory cells of the one or more groups of overhead data memory cells of the first block.

Claims (6)

1. A memory device, comprising:

a plurality of blocks of memory cells, each of the plurality of blocks of memory cells being individually erasable; and

a controller configured to configure a first block of the plurality of blocks of memory cells in a first configuration comprising one or more groups of overhead data memory cells, to configure a second block of the plurality of blocks of memory cells in a second configuration comprising a group of user data memory cells and a group of overhead data memory cells, and to configure a third block of the plurality of blocks of memory cells in a third configuration comprising only a group of user data memory cells;

wherein the first configuration is different than the second configuration and the third configuration is different than the first and second configurations;

wherein the group of overhead data memory cells of the second block of memory cells comprises a different storage capacity than at least one group of overhead data memory cells of the one or more groups of overhead data memory cells of the first block; and

wherein the controller being configured to configure the third block in the third configuration comprising only the group of user data memory cells comprises the controller being configured to store a portion of first user data in the group of user data memory cells of the third block, wherein the controller is configured to configure a fourth block of the plurality of blocks of memory cells in a fourth configuration, wherein the fourth configuration comprises a group of user data memory cells configured to store a remaining portion of the first user data, a group of overhead data memory cells configured to store overhead data specific to the portion of the first user data stored in the group of user data memory cells of the third block and the remaining portion of the first user data stored in the group of user data memory cells in the fourth block, and a group of user data memory cells configured to store second user data.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050702/0451 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 4 TO PATENT SECURITY AGREEMENT Recorded May 4, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042405/0909 →