IP Library Granted Patent US 10,545,695
Granted Patent B2
US 10,545,695 · App. 15/434,503 · Granted Jan 28, 2020

Solid state drive controller

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Quick Facts
Patent No.
US 10,545,695
App. No.
15/434,503
Granted
Jan 28, 2020
Kind
B2
Abstract

A memory device may comprise circuitry to adjust between latency and throughput in transferring information through a memory port, wherein the circuitry may be capable of configuring individual partitions or individual sectors as high-throughput storage or low-latency storage.

Claims (43)

1. An apparatus, comprising:

a memory port comprising a plurality of channels coupled to a memory array that is at least partially interchangeably configurable as high-throughput or low-latency; and

a controller coupled to the memory port and configured to:

determine whether a received request is a configuration request comprising instructions to configure a portion of the memory array associated with a subset of the channels as high-throughput or low-latency; and

responsive to determining that the received request is a configuration request:

configure the portion of the memory array as high-throughput or low-latency according to the configuration request;

update a configuration table according to the configuration request;

responsive to the configuration request comprising instructions to configure the portion of the memory array as low-latency, distribute information to a greater quantity of the channels to reduce latency; and

responsive to the configuration request comprising instructions to configure the portion of the memory array as high-throughput, distribute information to a lesser quantity of the channels to increase throughput.

2. The apparatus of claim 1 , wherein the controller is configured to distribute requests to either the greater quantity of the channels or the lesser quantity of the channels on a partition-by-partition basis.

3. The apparatus of claim 1 , wherein the controller is configured to distribute requests to either the greater quantity of the channels or the lesser number of the channels on a sector-by-sector basis.

4. The apparatus of claim 1 , wherein the controller is configured to store configuration information for the memory array.

5. A method, comprising:

determining whether a received request is a configuration request comprising instructions to configure at least one portion of a memory array as high-throughput or low-latency,

wherein the at least one portion of the memory array is associated with at least one channel of a memory port coupled to the memory array, and

wherein the memory array is at least partially interchangeably configurable as high-throughput or low-latency; and

responsive to determining that the received request is a configuration request:

configuring individual portions of the memory array associated with a plurality of channels of the memory port and the configuration request as high-throughput or low-latency according to the configuration request; and

updating a configuration table according to the configuration request.

6. The method of claim 5 , further comprising:

responsive to the configuration request comprising instructions to configure the individual portions of the memory array as low-latency, selectively increasing a quantity of the channels to which information is distributed to reduce latency; and

responsive to the configuration request comprising instructions to configure the portion of the memory array as high-throughput, selectively decreasing a quantity of the channels to which information is distributed to increase throughput.

7. The method of claim 6 , further comprising distributing information to an increased quantity of the channels or a decreased quantity of the channels according to the configuration request on a drive-wide basis.

8. The method of claim 6 , further comprising distributing information to an increased quantity of the channels or a decreased quantity of the channels according to the configuration request on a partition-by-partition basis.

9. The method of claim 6 , further comprising distributing information to an increased quantity of the channels or a decreased quantity of the channels according to the configuration request on a sector-by-sector basis.

10. The method of claim 5 , further comprising storing configuration information indicative of portions of the memory array configured as low-latency.

11. The method of claim 5 , further comprising storing configuration information indicative of portions of the memory array configured as high-throughput.

12. The method of claim 5 , further comprising receiving user input of the configuration request through an application from a host.

13. The method of claim 5 , further comprising receiving user input of the configuration request through a driver from a host.

14. An apparatus comprising:

a memory array, wherein the memory array is accessible through a memory port comprising a plurality of channels and at least partially interchangeably configurable as high-throughput or low-latency; and

a controller coupled to the memory array and configured to:

determine whether a received request is a configuration request comprising instructions to configure a portion of the memory array associated with a subset of the channels as high-throughput or low-latency; and

responsive to determining that the received request is a configuration request:

configure the portion of the memory array as high-throughput or low-latency according to the configuration request; and

update a configuration table according to the received configuration request.

15. The apparatus of claim 14 , wherein the memory array and the controller comprise a solid state drive (SSD).

16. The apparatus of claim 14 , wherein the controller is configured to store configuration information for the memory array.

17. The apparatus of claim 14 , further comprising a processor hosting applications to initiate memory requests to access the memory array through the controller.

18. The apparatus of claim 17 , wherein the applications provide a user input of the configuration request.

19. The apparatus of claim 14 , wherein the controller is configured to:

responsive to the configuration request comprising instructions to configure the portion of the memory array as low-latency, distribute information into a single one of the channels of the memory port; and

responsive to the configuration request comprising instructions to configure the portion of the memory array as high-throughput, distribute information into all the channels of the memory port.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050702/0451 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 4 TO PATENT SECURITY AGREEMENT Recorded May 4, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042405/0909 →