MEMORY PROTOCOL WITH PROGRAMMABLE BUFFER AND CACHE SIZE
The present disclosure includes apparatuses and methods related to a memory protocol with programmable buffer and cache size. An example apparatus can program a resister to define a size of a buffer in memory, store data in the buffer in a first portion of the memory defined by the register, and store data in a cache in a second portion of the memory.
1 . An apparatus, comprising:
a memory device; and
a controller coupled to the memory device configured to:
program a register to define a size of a buffer in memory;
store data in the buffer in a first portion of the memory defined by the register; and
store data in a cache in a second portion of the memory.
2 . The apparatus of claim 1 , wherein the memory device is a non-volatile dual in-line memory module (NVDIMM) device.
3 . The apparatus of claim 1 , wherein the memory is comprised of the first portion of the memory and the second portion of the memory.
4 . The apparatus of claim 1 , wherein the controller is configured to program another register that indicates the density of the memory.
5 . The apparatus of claim 4 , wherein the buffer and the cache are located on the controller.
6 . The apparatus of claim 1 , wherein the buffer and the cache are located on a memory array of the memory device.
7 . The apparatus of claim 6 , wherein the memory array is a DRAM memory array.
8 . An apparatus, comprising:
a controller on a memory module;
a first memory array on the memory module, the first memory array including a plurality of non-volatile memory cells; and
a second memory array on the memory module, the second memory module including a plurality of volatile memory cells;
wherein the controller comprises a register configured to determine an amount of the plurality of volatile memory cells of the second memory array to store at least one of buffer data and cache data for the first memory array.
9 . The apparatus of claim 8 , wherein the buffer data includes command data to be performed on the first memory array and the cache data includes data stored in the first memory array.
10 . The apparatus of claim 8 , wherein the controller, the first memory array, and the second memory array are arranged independently in a first chip, a second chip, and a third chip.
11 . The apparatus of claim 10 , wherein the first memory array and the second memory array are arranged in a first chip and the controller is arranged in a second chip.
12 . The apparatus of claim 10 , further comprising:
a third memory array on the memory module, the third memory array including a plurality of non-volatile memory cells; and
a fourth memory array on the memory module, the fourth memory array including a plurality of volatile memory cells;
wherein the register is further configured to determine an amount of the plurality of volatile memory cells of the fourth memory array to store at least one of buffer data and cache data for the third memory array; and
wherein the third memory array and the fourth memory array are arranged in a third chip.
13 . The apparatus of claim 8 , wherein the controller comprises a fifth memory array including a plurality of volatile memory cells different in memory cell type from the plurality of volatile memory cells of the second and fourth memory arrays.
14 . A method, comprising:
storing a number of entries in a buffer in memory, wherein a size of the buffer is determined by a register; and
storing data in a cache in memory, wherein a size of the cache is based on amount of memory remaining that is not used as the buffer.
15 . The method of claim 14 , furthering including programming a first buffer to define the size of the buffer.
16 . The method of claim 14 , further including programming a second buffer to define a density of the memory.
17 . The method of claim 14 , further including also storing the data in the cache in a non-volatile memory array of a non-volatile dual in-line memory module (NVDIMM) device.
18 . The method of claim 14 , further including storing the number of entries in the buffer in memory located on a controller.
19 . The method of claim 14 , further including storing the number of entries in the buffer in memory located on a volatile memory array of a non-volatile dual in-line memory module (NVDIMM) device.
20 . A method, comprising:
programming a register to define a size of a first portion of memory that is implemented as a buffer and a size of a second portion of the memory that is implemented as cache.
21 . The method of claim 20 , further including performing operations on a non-volatile dual in-line memory module (NVDIMM) device that use a buffer.
22 . The method of claim 20 , further including reprogramming the register to change the size of the first portion of the memory that is implemented as a buffer and the size of the second portion of the memory that is implemented as cache.
23 . The method of claim 20 , wherein programming the register to define the size of the first portion of memory that is implemented as the buffer is based on a threshold number of entries in the buffer.
24 . The method of claim 20 , wherein programming the register to define the size of the first portion of memory that is implemented as the buffer is based on a block size for a memory array of a non-volatile dual in-line memory module (NVDIMM) device.
25 . The method of claim 20 , further including programming the register to define the size of the first portion of memory located on a controller.
26 . The method of claim 20 , wherein on memory array further including programming the register to define the size of the first portion of memory located in a memory array of a non-volatile dual in-line memory module (NVDIMM) device.