Self-reference for ferroelectric memory
View Patent ↗Methods, systems, and apparatuses for self-referencing memory cells are described. A reference value for a cell may be created through multiple sense operations on the cell. The cell may be sensed several times and an average of at least two sensing operations may be used as a reference for another sense operation. For example, the cell may be sensed and the resulting charge stored at a capacitor. The cell may be biased to one state, sensed a second time, and the resulting charge stored at another capacitor. The cell may be biased to another state, sensed a third time, and the resulting charge stored to another capacitor. The values from the second and third sensing operations may be averaged and used as a reference value in a comparison with value of the first sensing operation to determine a logic state of the cell.
1. A method, comprising:
applying a first voltage to a ferroelectric memory cell to initiate a plurality of sense operations, wherein a first sense operation of the plurality of sense operations comprises applying the first voltage to the ferroelectric memory cell to extract a first charge from the ferroelectric memory cell and storing the first charge associated with the first sense operation at a first sense capacitor,
wherein a second sense operation of the plurality of sense operations comprises applying the first voltage to the ferroelectric memory cell to extract a second charge from the ferroelectric memory cell and storing the second charge associated with the second sense operation at a second sense capacitor, and
wherein a third sense operation of the plurality of sense operations comprises applying a second voltage to the ferroelectric memory cell, wherein a polarity of the second voltage is opposite of a polarity of the first voltage, removing the second voltage applied to the ferroelectric memory cell, applying the first voltage to the ferroelectric memory cell to extract a third charge from the ferroelectric memory cell, and storing the third charge associated with the third sense operation at a third sense capacitor;
determining a reference voltage for the ferroelectric memory cell based at least in part on an average of two sense operations of the plurality;
identifying a signal that is a function of the reference voltage and a sensed voltage of an additional sense operation of the plurality of sense operations; and
determining a logic state of the ferroelectric memory cell based at least in part on the signal.
2. The method of claim 1 , further comprising:
averaging a voltage of the second sense capacitor due to the second charge with a voltage of the third sense capacitor due to the third charge, wherein the reference voltage is based at least in part on the averaging.
3. The method of claim 2 , wherein the signal is a function of the reference voltage and the first charge stored at the first sense capacitor.
4. The method of claim 1 , wherein applying the first voltage to the ferroelectric memory cell to initiate the plurality of sense operations comprises:
selecting the ferroelectric memory cell using a switching component.
5. The method of claim 4 , further comprising:
activating the switching component; and
applying a voltage to the ferroelectric memory cell based at least in part on the activation of the switching component, wherein applying the voltage to the ferroelectric memory cell initializes the ferroelectric memory cell to a first state or a second state.
6. The method of claim 1 , further comprising:
writing a logic value to the ferroelectric memory cell, wherein the logic value is based at least in part on the signal and a charge associated with at least one of the plurality of sense operations.
7. An electronic memory apparatus, comprising:
a ferroelectric memory cell in electronic communication with a digit line;
a plurality of sense capacitors in electronic communication with the digit line via a plurality of switching components; and
a controller in electronic communication with and the plurality of sense capacitors, wherein the controller is operable to:
apply a first voltage to the ferroelectric memory cell to initiate a plurality of sense operations;
determine a reference voltage for the ferroelectric memory cell based at least in part on an average of two sense operations of the plurality; and
determine a logic state of the ferroelectric memory cell based at least in part on a comparison of the reference voltage and a sensed voltage of an additional sense operation of the plurality of sense operations.
8. The electronic memory apparatus of claim 7 , wherein:
a first sense capacitor of the plurality is coupled with the digit line via a first switching component and coupled with a sense component via a second switching component;
a second sense capacitor of the plurality is coupled with the digit line via a third switching component and coupled with the sense component via a fourth switching component; and
a third sense capacitor of the plurality is coupled with the digit line via a fifth switching component and coupled with the sense component via a sixth switching component.
9. The electronic memory apparatus of claim 8 , wherein the controller is operable to control the first switching component, the third switching component, and the fifth switching component to:
store a first charge associated with a first sense operation of the plurality at the first sense capacitor;
store a second charge associated with a second sense operation of the plurality at the second sense capacitor; and
store a third charge associated with a third sense operation of the plurality at the third sense capacitor.
10. The electronic memory apparatus of claim 9 , wherein the controller is operable to:
set a first condition of the ferroelectric memory cell after extracting the first charge associated with the first sense operation;
set a second condition of the ferroelectric memory cell after extracting the second charge associated with the second sense operation; and
reset the first condition of the ferroelectric memory cell after extracting the third charge associated with the third sense operation.
11. The electronic memory apparatus of claim 9 , wherein the controller is operable to control the second switching component, the fourth switching component, and the sixth switching component to:
determine the reference voltage; and
compare the reference voltage and the sensed voltage of the additional sense operation.