Apparatuses and methods including memory access in cross point memory
View Patent ↗Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments. the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
1. An apparatus comprising:
a first memory array including first memory cells and a first group of conductive lines configured to access the first memory cells;
a second memory array including second memory cells and a second group of conductive lines configured to access the second memory cells;
a first group of transistors coupled to the first group of conductive lines, the first group of transistors configured to respond to a first signal;
a first switching circuit configured to apply a signal to a selective conductive line of the first group of conductive lines, wherein the first switching circuit includes a phase change material;
a second group of transistors coupled to the second group of conductive lines, the second group of transistors configured to respond to a second signal; and
a second switching circuit configured to apply the signal to a selective conductive line of the second group of conductive lines, wherein the second switching circuit includes a phase change material.
2. The apparatus of claim 1 , wherein the first switching circuit includes a first group of switches, and each switch in the first group of switches includes an electrode coupled to a respective conductive line of the first group of conductive lines.
3. The apparatus of claim 2 , wherein the second switching circuit includes a second group of switches, and each switch in the second group of switches includes an electrode coupled to a respective conductive line of the second group of conductive lines.
4. The apparatus of claim 1 , wherein the first group of transistors is configured to turn on when the second group of transistors turns off, and the first group of transistors is configured to turn off when the second group of transistors turns on.
5. The apparatus of claim 1 , further comprising a substrate, wherein the first memory array overlies the substrate and the second memory array overlies the first memory array.
6. The apparatus of claim 5 , wherein at least one of the first and second groups of transistors is located in the substrate.
7. An apparatus comprising:
a first memory array including first phase change memory cells and a first group of conductive lines configured to access the first phase change memory cells;
a second memory array including second phase change memory cells and a second group of conductive lines configured to access the second phase change memory cells;
additional lines shared by the first and second phase change memory cells;
a first group of transistors coupled to the first group of conductive lines, the first group of transistors configured to respond to a first signal;
a first switching circuit configured to apply a signal to a selective conductive line of the first group of conductive lines;
a second group of transistors coupled to the second group of conductive lines, the second group of transistors configured to respond to a second signal; and
a second switching circuit configured to apply the signal to a selective conductive line of the second group of conductive lines.
8. The apparatus of claim 7 , further comprising a substrate, wherein the additional lines and the first and second group of conductive lines are located over the substrate, and the first and second phase change memory cells are located between the additional lines and the first and second group of conductive lines.
9. The apparatus of claim 8 , wherein the additional lines extend in a first direction, and the first and second group of conductive lines extend in a second direction.
10. The apparatus of claim 7 , wherein the additional lines are located between the substrate and the first and second phase change memory cells.
11. The apparatus of claim 7 , wherein:
the first switching circuit includes a first group of switches, and a switch in the first group of switches is coupled between a conductive line of the first group of conductive lines an additional line of the additional lines; and
the second switching circuit includes a second group of switches, and a switch in the second group of switches is coupled between a conductive line of the second group of conductive lines the additional line of the additional lines.
12. The apparatus of claim 7 , wherein:
a phase change memory cell of the first phase change memory cells is coupled between a conductive line of the first group of conductive lines an additional line of the additional lines; and
a phase change memory cell of the second phase change memory cells is coupled between a conductive line of the second group of conductive lines the additional line of the additional lines.
13. The apparatus of claim 7 , wherein the first switching circuit includes a first group of switches, each switch in the first group of switches includes an electrode coupled to a respective conductive line of the first group of conductive lines.
14. The apparatus of claim 7 , wherein the second switching circuit includes a second group of switches, each switch in the second group of switches includes an electrode coupled to a respective conductive line of the second group of conductive lines.
15. The apparatus of claim 7 , wherein the first signal is configured to be provided with a first voltage during a memory operation of the apparatus, and the second signal is configured to be provided with a second voltage during the memory operation of the apparatus.
16. An apparatus comprising:
a first memory array including first phase change memory cells and a first group of conductive lines configured to access the first phase change memory cells;
a second memory array including second phase change memory cells and a second group of conductive lines configured to access the second phase change memory cells;
additional lines shared by the first and second phase change memory cells;
a first group of transistors coupled to the first group of conductive lines, the first group of transistors configured to respond to a first signal;
a first switching circuit configured to apply a signal to a selective conductive line of the first group of conductive lines, wherein the first switching circuit includes a phase change material, wherein the first switching circuit includes a phase change material;
a second group of transistors coupled to the second group of conductive lines, the second group of transistors configured to respond to a second signal; and
a second switching circuit configured to apply the signal to a selective conductive line of the second group of conductive lines, wherein the second switching circuit includes a phase change material, wherein the second switching circuit includes a phase change material.
17. The apparatus of claim 16 , wherein the additional lines are perpendicular to the first and second group of conductive lines.
18. The apparatus of claim 16 , wherein the first and second signals are configured to be provided with different voltages during a memory operation of the apparatus.
19. The apparatus of claim 16 , wherein:
the first switching circuit includes a first group of switches, and a switch in the first group of switches is coupled between a conductive line of the first group of conductive lines an additional line of the additional lines; and
the second switching circuit includes a second group of switches, and a switch in the second group of switches is coupled between a conductive line of the second group of conductive lines the additional line of the additional lines.
20. The apparatus of claim 19 , wherein:
a phase change memory cell of the first phase change memory cells is coupled between the conductive line of the first group of conductive lines the additional line of the additional lines; and
a phase change memory cell of the second phase change memory cells is coupled between the conductive line of the second group of conductive lines the additional line of the additional lines.