IP Library Granted Patent US 9,899,254
Granted Patent B2
US 9,899,254 · App. 15/471,420 · Granted Feb 20, 2018

Forming array contacts in semiconductor memories

Inventors: Roberto Somaschini (Vimercate, IT); Alessandro Vaccaro (Boise, ID); Paolo Tessariol (Montevelluna, IT); Giulio Albini (Boise, ID)
Assignee: Micron Technology, Inc.
H01L21/76807H01L21/7684H01L21/76877H01L27/1052
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Quick Facts
Patent No.
US 9,899,254
App. No.
15/471,420
Granted
Feb 20, 2018
Kind
B2
Abstract

Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

Claims (29)

1. A method comprising:

filling a plurality of trenches formed in a dielectric layer with a filler material over an etch stop layer;

forming a plurality of masks extending perpendicularly a length of a plurality of filled trenches;

removing exposed portions of the plurality of filled trenches, until the etch stop layer, to form openings in the plurality of filled trenches; and

filling the openings to form contacts.

2. The method of claim 1 , wherein removing exposed portions of the plurality of filled trenches, until the etch stop layer, comprises etching the exposed portions until the etch stop layer.

3. The method of claim 1 , wherein the etch stop layer is defined in the dielectric layer.

4. The method of claim 1 , further comprising removing the plurality of masks.

5. The method of claim 4 , wherein removing the plurality of masks comprises tapering the filled trenches.

6. The method of claim 5 , wherein the contacts have tapered side walls.

7. The method of claim 6 , further comprising forming a metal line and the contacts in the same metallization.

8. The method of claim 5 , wherein the filled trenches taper inwardly from a top of the filled trenches to a bottom of the filled trenches.

9. The method of claim 1 , wherein the etch stop layer is at a bottom of the dielectric layer.

10. The method of claim 1 , wherein the etch stop layer comprises a borderless nitride.

11. The method of claim 1 , further comprising forming parallel spaced active areas and forming the plurality of filled trenches perpendicular to the active areas.

12. A method comprising:

filling a trench formed in a dielectric layer;

forming a plurality of spaced openings along a length of a trench of a plurality of parallel spaced filled trenches over a memory array; and

forming array contacts in the plurality of spaced openings.

13. The method of claim 12 , wherein the plurality of parallel spaced filled trenches are formed in the dielectric layer over the memory array.

14. The method of claim 12 , wherein filling the trench formed in the dielectric layer comprises forming the dielectric layer with a stop layer to stop an etching process.

15. The method of claim 12 , further comprising forming a plurality of parallel spaced masks extending transversely to the plurality of parallel spaced filled trenches prior to forming the plurality of spaced openings along the length of the trench of the plurality of parallel spaced filled trenches.

16. The method of claim 12 , further comprising removing an upper portion of the plurality of parallel spaced filled trenches.

17. The method of claim 16 , wherein removing the upper portion of the plurality of parallel spaced filled trenches comprises removing the upper portion until a stop layer.

18. The method of claim 16 , wherein the stop layer is a part of the dielectric layer.

19. The method of claim 16 , wherein removing the upper portion of the plurality of parallel spaced filled trenches comprises etching the upper portion until a stop layer.

20. The method of claim 12 , further comprising:

forming parallel spaced active areas; and

forming the plurality of parallel spaced filled trenches perpendicular to the parallel spaced active areas.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050702/0451 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 4 TO PATENT SECURITY AGREEMENT Recorded May 4, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042405/0909 →
Continuity (5)
Continuation 14722889 · May 27, 2015
Continuation 14302160 · Jun 11, 2014
Continuation 14066340 · Oct 29, 2013
Division 12724491 · Mar 16, 2010
Related Publication 20170200635A1 · Jul 13, 2017