Memory device including pass transistors in memory tiers
Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes a semiconductor material, a pillar extending through the semiconductor material, a select gate located along a first portion of the pillar, memory cells located along a second portion of the pillar, and transistors coupled to the select gate through a portion of the semiconductor material. The transistors include sources and drains formed from portions of the semiconductor material. The transistors include gates that are electrically uncoupled to each other.
1. An apparatus comprising:
a piece of semiconductor material formed over a substrate;
a pillar extending through the piece of semiconductor material;
a select gate located along a first portion of the pillar;
memory cells located along a second portion of the pillar; and
transistors coupled to the select gate through a portion of the piece of semiconductor material, the transistors including sources and drains, the transistors including gates electrically uncoupled to each other, and at least a portion of the piece of semiconductor material forms the sources and drains of the transistors, and a portion of the select gate.
2. The apparatus of claim 1 , wherein the piece of semiconductor material includes an additional portion configured to form a select line to control the select gate.
3. The apparatus of claim 1 , wherein the piece of semiconductor material includes n-type polycrystalline silicon.
4. The apparatus of claim 1 , further comprising:
a first additional pillar extending through the piece of semiconductor material, wherein a portion of the first additional pillar forms a first portion of a gate structure of a transistor of the transistors; and
a second additional pillar extending through the piece of semiconductor material, wherein a portion of the second additional pillar forms a second portion of the gate structure of the transistor of the transistors, and the first and second additional pillars are electrically coupled to each other.
5. An apparatus comprising:
pieces of semiconductor materials located in different levels of the apparatus;
a pillar extending through the pieces of semiconductor materials;
a select gate located along a first portion of the pillar;
memory cells located along a second portion of the pillar;
a first additional pillar extending through the pieces of semiconductor materials;
first transistors located along a portion of the first additional pillar, the first additional pillar including a first piece of conductive material to form a gate of each of the first transistors;
a second additional pillar extending through the pieces of semiconductor materials; and
second transistors located along a portion of the second additional pillar, the second additional pillar including a second piece of conductive material to form a gate of each of the second transistors, the pieces of semiconductor materials including a piece of semiconductor material, a portion of the piece of semiconductor material forming:
a source and a drain of a transistor of the first transistors;
a source and drain of a transistor of the second transistors; and
a portion of the select gate.
6. The apparatus of claim 5 , further comprising:
a third additional pillar extending through the piece of semiconductor materials; and
third transistors located along a portion of the third additional pillar, the third additional pillar including a third piece of conductive material to form a gate of each of the third transistors.
7. The apparatus of claim 5 , further comprising a conductive source, wherein the pillar includes a piece of conductive material coupled to the conductive source, the first piece of conductive material of the first additional pillar is electrically uncoupled to the conductive source, and the second piece of conductive material of the second additional pillar is electrically uncoupled to the conductive source.
8. An apparatus comprising:
pieces of semiconductor materials located in different levels of the apparatus;
a pillar extending through the pieces of semiconductor materials;
a select gate located along a first portion of the pillar;
memory cells located along a second portion of the pillar;
a first additional pillar extending through a first piece of semiconductor material of the pieces of semiconductor materials;
a first transistor located along a first portion of first additional pillar, a first portion of the first piece of semiconductor material forming a source of the first transistor, a second portion of the first piece of semiconductor material forming a drain of the first transistor, the first additional pillar including a first piece of conductive material forming a gate of the first transistor;
a second additional pillar extending through the first piece of semiconductor material; and
a second transistor located along a first portion of the second additional pillar, a third portion of the first piece of semiconductor material forming a source of the second transistor, a fourth portion of the first piece of semiconductor material forming a drain of the second transistor, and the second additional pillar including a second piece of conductive material forming a gate of the second transistor.
9. The apparatus of claim 8 , further comprising:
a third additional pillar extending through the first piece of semiconductor material of the pieces of semiconductor materials; and
a third transistor located along a first portion of the third additional pillar, a fifth portion of the first piece of semiconductor material forming a source of the third transistor, a sixth portion of the first piece of semiconductor material forming a drain of the third transistor, and the third additional pillar including a third piece of conductive material forming a gate of the third additional transistor.
10. The apparatus of claim 8 , wherein each of the first and second additional pillars also extends through a second piece of semiconductor material of the pieces of semiconductor materials, and the apparatus further comprises:
a first additional transistor located along a second portion of the first additional pillar, a first portion of the second piece of semiconductor material forming a source of the first additional transistor, a second portion of the second piece of semiconductor material forming a drain of the first additional transistor, and the first piece of conductive material of the first additional pillar also forming a gate of the first additional transistor; and
a second additional transistor located along a second portion of the second additional pillar, a third portion of the second piece of semiconductor material forming a source of the second additional transistor, a fourth portion of the second piece of semiconductor material forming a drain of the second additional transistor, and the second piece of conductive material of the second additional pillar also forming a gate of the second additional transistor.
11. The apparatus of claim 10 , further comprising:
a third additional pillar extending through the first and second pieces of semiconductor materials;
a third transistor located along a first portion of the third additional pillar, a fifth portion of the first piece of semiconductor material forming a source of the third transistor, a sixth portion of the first piece of semiconductor material forming a drain of the third transistor, the third additional pillar including a third piece of conductive material forming a gate of the third transistor; and
a third additional transistor located along a second portion of the third additional pillar, a fifth portion of the second piece of semiconductor material forming a source of the third additional transistor, a sixth portion of the second piece of semiconductor material forming a drain of the third additional transistor, and the third piece of conductive material also forming a gate of the third additional transistor.