Operation of mixed mode blocks
Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.
1. An apparatus, comprising:
a memory comprising mixed mode blocks of memory cells; and
a controller coupled to the memory and configured to:
track single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks;
maintain a mixed mode cycle count corresponding to the mixed mode blocks; and
adjust the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed mode blocks operated in a XLC mode, wherein the controller being configured to adjust the mixed mode cycle count includes the controller being configured to increment the mixed mode cycle count, and wherein an increment difference between SLC mode cycles and XLC mode cycles is based on a determined wear ratio of SLC operation wear to XLC operation wear.
2. The apparatus of claim 1 , wherein the mixed mode cycle count is a scaled cycle count having a different value than an actual quantity of physical cycles performed on the mixed mode blocks.
3. The apparatus of claim 1 , wherein the controller is configured to perform wear leveling based on the mixed mode cycle count as opposed to based on an unscaled cycle count corresponding to a quantity of actual physical cycles experienced by the mixed mode blocks.
4. The apparatus of claim 1 , wherein the apparatus is a solid state drive (SSD).
5. The apparatus of claim 4 , wherein the controller is configured to report a drive health indicator of the SSD to a host based on the mixed mode cycle count as opposed to based on an unscaled cycle count corresponding to a quantity of actual physical cycles experienced by the mixed mode blocks.
6. The apparatus of claim 1 , wherein a difference by which the controller adjusts the mixed mode cycle count for mixed mode blocks operated in the SLC mode than for mixed mode blocks operated in the XLC mode is based on a wear ratio of SLC operation wear to XLC operation wear resulting from adjusted trim settings.
7. The apparatus of claim 6 , wherein the mixed mode cycle count is a mixed mode erase count.
8. The apparatus of claim 6 , wherein the mixed mode cycle count is a mixed mode program count.
9. An apparatus, comprising:
a memory comprising mixed mode blocks of memory cells; and
a controller coupled to the memory and configured to:
track single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks;
maintain a mixed mode cycle count corresponding to the mixed mode blocks; and
adjust the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed mode blocks operated in a XLC mode, wherein the mixed mode cycle count is a scaled cycle count having a different value than an actual quantity of physical cycles performed on the mixed mode blocks.
10. An apparatus, comprising:
a memory comprising mixed mode blocks of memory cells; and
a controller coupled to the memory and configured to:
track single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks;
maintain a mixed mode cycle count corresponding to the mixed mode blocks;
adjust the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed mode blocks operated in a XLC mode; and
perform wear leveling based on the mixed mode cycle count as opposed to based on an unscaled cycle count corresponding to a quantity of actual physical cycles experienced by the mixed mode blocks.
11. A solid state drive (SSD), comprising:
a memory comprising mixed mode blocks of memory cells; and
a controller coupled to the memory and configured to:
track single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks;
maintain a mixed mode cycle count corresponding to the mixed mode blocks;
adjust the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed mode blocks operated in a XLC mode; and
report a drive health indicator of the SSD to a host based on the mixed mode cycle count as opposed to based on an unscaled cycle count corresponding to a quantity of actual physical cycles experienced by the mixed mode blocks.
12. An apparatus, comprising:
a memory comprising mixed mode blocks of memory cells; and
a controller coupled to the memory and configured to:
track single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks;
maintain a mixed mode cycle count corresponding to the mixed mode blocks; and
adjust the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed mode blocks operated in a XLC mode, wherein a difference by which the controller adjusts the mixed mode cycle count for mixed mode blocks operated in the SLC mode than for mixed mode blocks operated in the XLC mode is based on a wear ratio of SLC operation wear to XLC operation wear resulting from adjusted trim settings.
13. The apparatus of claim 12 , wherein the mixed mode cycle count is a mixed mode erase count.
14. The apparatus of claim 12 , wherein the mixed mode cycle count is a mixed mode program count.