Microprocessor architecture having alternative memory access paths
The present invention is directed to a system and method which employ two memory access paths: 1) a cache-access path in which block data is fetched from main memory for loading to a cache, and 2) a direct-access path in which individually-addressed data is fetched from main memory. The system may comprise one or more processor cores that utilize the cache-access path for accessing data. The system may further comprise at least one heterogeneous functional unit that is operable to utilize the direct-access path for accessing data. In certain embodiments, the one or more processor cores, cache, and the at least one heterogeneous functional unit may be included on a common semiconductor die (e.g., as part of an integrated circuit). Embodiments of the present invention enable improved system performance by selectively employing the cache-access path for certain instructions while selectively employing the direct-access path for other instructions.
1. A memory system providing memory access for a multiple processor system including at least one processor and at least one heterogeneous functional unit, the at least one processor configured to execute at least one instruction of a first instruction set and the at least one heterogeneous functional unit configured to execute at least one instruction of a second instruction set that is different than the first instruction set, the memory system comprising:
a main memory configured for individually-addressed data access;
a block oriented cache-access path coupling the main memory and a cache memory, wherein the block oriented cache-access path is configured to provide fixed-size data block access to the main memory, and wherein the cache memory provides storage of fixed-size data blocks of main memory data for data access by the at least one processor; and
an address oriented cache-bypass path coupling the main memory and the at least one heterogeneous functional unit, wherein the address oriented cache-bypass path provides individually-addressed data access to the main memory.
2. The memory system of claim 1 , wherein the fixed-size data block access to the main memory returns data in addition to data referenced by a cache memory access by the at least one processor, and wherein the individually-addressed data access returns only data referenced by a physical address access by the at least one heterogeneous functional unit.
3. The memory system of claim 1 , wherein the main memory is configured to emulate block data access for the block oriented cache-access path.
4. The memory system of claim 1 , wherein the main memory comprises a scatter/gather memory module.
5. The memory system of claim 1 , further comprising:
a cache interrogation path coupling the cache memory and the heterogeneous functional unit, wherein the cache interrogation path is configured to provide information regarding encached data to the heterogeneous functional unit in response to an interrogation by the heterogeneous functional unit regarding referenced data to be accessed by the heterogeneous functional unit.
6. The memory system of claim 5 , wherein the cache interrogation path is configured initiate writing a cache block containing the referenced data to the main memory for individually-addressed data access of the referenced data from the main memory by the heterogeneous functional unit using the address oriented cache-bypass path.
7. The memory system of claim 5 , wherein the cache interrogation path is configured to invalidate the referenced data in the cache memory in association with individually-addressed data access of the referenced data from the main memory by the heterogeneous functional unit using the address oriented cache-bypass path.
8. The memory system of claim 1 , wherein the at least one processor and the at least one heterogeneous functional unit comprise different instruction sets.
9. A method comprising:
providing fixed-size data block access to a main memory by at least one processor of a multiple processor system including the at least one processor and at least one heterogeneous functional unit via a block oriented cache-access path coupling the main memory and a cache memory, the at least one processor configured to execute at least one instruction of a first instruction set and the at least one heterogeneous functional unit configured to execute at least one instruction of a second instruction set that is different than the first instruction set, wherein the cache memory provides storage of fixed-size data blocks of main memory data for data access by the at least one processor; and
providing individually-addressed data access to the main memory by the at least one heterogeneous functional unit of the multiple processor system via an address oriented cache-bypass path coupling the main memory and the at least one heterogeneous functional unit.
10. The method of claim 9 , wherein the fixed-size data block access to the main memory returns data in addition to data referenced by a cache memory access by the at least one processor, and wherein the individually-addressed data access returns only data referenced by a physical address access by the at least one heterogeneous functional unit.
11. The method of claim 9 , wherein the main memory comprises scatter/gather memory configured for individually-addressed data access, and wherein the providing fixed-size data block access to the main memory comprises:
emulating block data access to the main memory for the block oriented cache-access path.
12. The method of claim 9 , further comprising:
providing information regarding data encached in the cache memory to the heterogeneous functional unit in response to an interrogation by the heterogeneous functional unit regarding referenced data to be accessed by the heterogeneous functional unit.
13. The method of claim 12 , further comprising:
writing a cache block containing the referenced data to the main memory for individually-addressed data access of the referenced data from the main memory by the heterogeneous functional unit.
14. The method of claim 12 , further comprising:
invalidating the referenced data in the cache memory in association with individually-addressed data access of the referenced data from the main memory by the heterogeneous functional unit.
15. The method of claim 9 , wherein the at least one processor and the at least one heterogeneous functional unit comprise different instruction sets.
16. The method of claim 9 , further comprising:
off-loading an instruction from a processor of the at least one processor to a heterogeneous functional unit of the at least one heterogeneous functional unit so that the heterogeneous functional unit takes advantage of the address oriented cache-bypass path to access the main memory using the individually-addressed data access for processing the off-loaded instruction.
17. A system comprising:
at least one processor configured to execute at least one instruction of a first instruction set;
at least one heterogeneous functional unit configured to execute at least one instruction of a second instruction set that is different than the first instruction set;
a main memory configured for individually-addressed data access and for fixed-size data block access;
a cache memory configured to provide storage of fixed-size data blocks of main memory data for data access by the at least one processor;
a block oriented cache-access path coupling the main memory and the cache memory, wherein the block oriented cache-access path is configured to provide fixed-size data block access to the main memory; and
an address oriented cache-bypass path coupling the main memory and the at least one heterogeneous functional unit, wherein the address oriented cache-bypass path provides individually-addressed data access to the main memory.
18. The system of claim 17 , further comprising:
a cache interrogation path coupling the cache memory and the heterogeneous functional unit, wherein the cache interrogation path is configured to provide information regarding encached data to the heterogeneous functional unit in response to an interrogation by the heterogeneous functional unit regarding referenced data to be accessed by the heterogeneous functional unit.
19. The system of claim 18 , wherein the cache interrogation path is configured initiate writing a cache block containing the referenced data to the main memory for individually-addressed data access of the referenced data from the main memory by the heterogeneous functional unit using the address oriented cache-bypass path.
20. The system of claim 18 , wherein the cache interrogation path is configured to invalidate the referenced data in the cache memory in association with individually-addressed data access of the referenced data from the main memory by the heterogeneous functional unit using the address oriented cache-bypass path.